View PC48F4400P0VT00A_3771815.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

order number: 306666, revision: 005 08-feb-2006 intel strataflash ? embedded memory (p30) family datasheet product features the intel strataflash ? embedded memory (p30) product is the latest generation of intel strataflash ? memory devices. offered in 64-mbit up through 512-mbit densities, the p30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. benefits include more density in less space, high-speed interface, lowest cost-per-bit nor device, and support for code and data storage. features include high-performance synchronous- burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. the p30 product family is manufactured using intel ? 130 nm etox? viii process technology. high performance ? 85 ns initial access ? 40 mhz with zero wait states, 20 ns clock-to- data output synchronous-burst read mode ? 25 ns asynchronous-page read mode ? 4-, 8-, 16-, and continuous-word burst mode ? buffered enhanced factory programming (befp) at 5 s/byte (typ) ? 1.8 v buffered programming at 7 s/byte (typ) architecture ? multi-level cell technology: highest density at lowest cost ? asymmetrically-blocked architecture ? four 32-kbyte parameter blocks: top or bottom configuration ? 128-kbyte main blocks voltage and power ?v cc (core) voltage: 1.7 v ? 2.0 v ?v ccq (i/o) voltage: 1.7 v ? 3.6 v ? standby current: 55 a (typ) for 256-mbit ? 4-word synchronous read current: 13 ma (typ) at 40 mhz quality and reliability ? operating temperature: ?40 c to +85 c ? minimum 100,000 erase cycles per block ? etox? viii process technology (130 nm) security ? one-time programmable registers: ? 64 unique factory device identifier bits ? 64 user-programmable otp bits ? additional 2048 user-programmable otp bits ? selectable otp space in main array: ? four pre-defined 128-kbyte blocks (top or bottom configuration) ? absolute write protection: v pp = v ss ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down software ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ?intel ? flash data integrator optimized ? basic command set and extended command set compatible ? common flash interface capable density and packaging ? 64/128/256-mbit densities in 56-lead tsop package ? 64/128/256/512-mbit densities in 64-ball intel ? easy bga package ? 64/128/256/512-mbit densities in intel ? quad+ scsp ? 16-bit wide data bus
08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 2 order number: 306666, revision: 005 legal lines and disclaimers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. the intel strataflash ? embedded memory (p30) family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2006, intel corporation. all rights reserved.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 3 contents 1.0 introduction ............................................................................................................................... 7 1.1 nomenclature ................................................................................................................ ....... 7 1.2 acronyms.................................................................................................................... ..........7 1.3 conventions................................................................................................................. .........8 2.0 functional overview ..............................................................................................................9 3.0 package information ............................................................................................................10 3.1 56-lead tsop package..................................................................................................... 10 3.2 64-ball easy bga package ................................................................................................12 3.3 quad+ scsp packages.................................................................................................... 13 4.0 ballout and signal descriptions ......................................................................................16 4.1 signal ballout .............................................................................................................. ........16 4.2 signal descriptions ......................................................................................................... ....19 4.3 scsp configurations......................................................................................................... .22 4.4 memory maps ................................................................................................................. ....24 5.0 maximum ratings and operating conditions ...........................................................27 5.1 absolute maximum ratings ................................................................................................27 5.2 operating conditions ........................................................................................................ ..28 6.0 electrical specifications .....................................................................................................29 6.1 dc current characteristics .................................................................................................2 9 6.2 dc voltage characteristics.................................................................................................3 1 7.0 ac characteristics ................................................................................................................32 7.1 ac test conditions .......................................................................................................... ... 32 7.2 capacitance................................................................................................................. .......33 7.3 ac read specifications ...................................................................................................... 34 7.4 ac write specifications ..................................................................................................... .40 7.5 program and erase characteristics .................................................................................... 44 8.0 power and reset specifications .....................................................................................45 8.1 power up and down........................................................................................................... 45 8.2 reset specifications ........................................................................................................ ... 45 8.3 power supply decoupling...................................................................................................46 9.0 device operations .................................................................................................................47 9.1 bus operations .............................................................................................................. ..... 47 9.1.1 reads ....................................................................................................................4 7 9.1.2 writes.................................................................................................................... .48 9.1.3 output disable .......................................................................................................48 9.1.4 standby..................................................................................................................4 8 9.1.5 reset ..................................................................................................................... 48 9.2 device commands ............................................................................................................. 49 9.3 command definitions ......................................................................................................... 50
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 4 order number: 306666, revision: 005 10.0 read operations .................................................................................................................... 52 10.1 asynchronous page-mode read........................................................................................ 52 10.2 synchronous burst-mode read.......................................................................................... 52 10.3 read configuration register .............................................................................................. 53 10.3.1 read mode ............................................................................................................ 54 10.3.2 latency count........................................................................................................ 54 10.3.3 wait polarity......................................................................................................... 56 10.3.4 data hold............................................................................................................... 5 7 10.3.5 wait delay............................................................................................................58 10.3.6 burst sequence ..................................................................................................... 58 10.3.7 clock edge ............................................................................................................58 10.3.8 burst wrap............................................................................................................. 58 10.3.9 burst length .......................................................................................................... 59 11.0 programming operations .................................................................................................. 60 11.1 word programming........................................................................................................... .. 60 11.1.1 factory word programming................................................................................... 61 11.2 buffered programming....................................................................................................... .61 11.3 buffered enhanced factory programming ......................................................................... 62 11.3.1 befp requirements and considerations .............................................................. 62 11.3.2 befp setup phase................................................................................................ 63 11.3.3 befp program/verify phase ................................................................................. 63 11.3.4 befp exit phase ................................................................................................... 64 11.4 program suspend............................................................................................................ ... 64 11.5 program resume............................................................................................................. ... 65 11.6 program protection......................................................................................................... .... 65 12.0 erase operations ...................................................................................................................66 12.1 block erase................................................................................................................ ......... 66 12.2 erase suspend .............................................................................................................. .....66 12.3 erase resume............................................................................................................... ..... 67 12.4 erase protection ........................................................................................................... ......67 13.0 security modes ....................................................................................................................... 68 13.1 block locking.............................................................................................................. ........ 68 13.1.1 lock block ............................................................................................................. 68 13.1.2 unlock block .......................................................................................................... 68 13.1.3 lock-down block ................................................................................................... 68 13.1.4 block lock status .................................................................................................. 69 13.1.5 block locking during suspend.............................................................................. 69 13.2 selectable one-time programmable blocks......................................................................70 13.3 protection registers ....................................................................................................... .... 71 13.3.1 reading the protection registers .......................................................................... 72 13.3.2 programming the protection registers.................................................................. 72 13.3.3 locking the protection registers ...........................................................................72 14.0 special read states ............................................................................................................. 73 14.1 read status register....................................................................................................... ... 73 14.1.1 clear status register............................................................................................. 74 14.2 read device identifier ..................................................................................................... ... 74
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 5 14.3 cfi query .................................................................................................................. .........75 appendix a write state machine ..........................................................................................76 appendix b flowcharts ............................................................................................................83 appendix c common flash interface ................................................................................91 appendix d additional information ...................................................................................101 appendix e ordering information for discrete products ........................................102 appendix f ordering information for scsp products ..............................................103
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 6 order number: 306666, revision: 005 revision history revision date revision description april 2005 -001 initial release august 2005 -002 revised discrete memory maps in section 4.4, ?memory maps? on page 24 added memory maps for 512-mbit top parameter devices in section 4.4, ?memory maps? on page 24 fixed size of programming region for 256-mbit to be 8-mbit in section 4.4, ?memory maps? on page 24 and section 11.0, ?programming operations? on page 60 removed power supply sequencing requirement in section 8.1, ?power up and down? on page 45 updated conditions for table 13 ?capacitance? on page 33 updated cfi table in appendix c, ?common flash interface? september 2005 -003 added note to table 27 ?device id codes? on page 75 for stacked device id codes synchronous burst read operation is currently not supported for the tsop package updated 512-mbit easy bga ball height (symbol a1) in figure 2 ?easy bga mechanical specifications? on page 12 01-nov-2005 -004 updated read access speed for 265m tsop package 08-feb-2006 -005 removed all references to 1 gigabit.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 7 1.0 introduction this document provides information about the intel strataflash ? embedded memory (p30) device and describes its features, operation, and specifications. 1.1 nomenclature 1.2 acronyms 1.8 v: v cc (core) voltage range of 1.7 v ? 2.0 v 3.0 v: v ccq (i/o) voltage range of 1.7 v ? 3.6 v 9.0 v: v pp voltage range of 8.5 v ? 9.5 v block: a group of bits, bytes, or words within the flash memory array that erase simultaneously when the erase command is issued to the device. the intel strataflash ? embedded memory (p30) family has two block sizes: 32-kbyte and 128-kbyte. main block: an array block that is usually used to store code and/or data. main blocks are larger than parameter blocks. parameter block: an array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in eeprom. top parameter device: a device with its parameter blocks located at the highest physical address of its memory map. bottom parameter device: a device with its parameter blocks located at the lowest physical address of its memory map. befp: buffer enhanced factory programming cui: command user interface mlc: multi-level cell otp: one-time programmable plr: protection lock register pr: protection register rcr: read configuration register rfu: reserved for future use sr: status register wsm: write state machine
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 8 order number: 306666, revision: 005 1.3 conventions vcc: signal or voltage connection v cc : signal or voltage level 0x: hexadecimal number prefix 0b: binary number prefix sr[4]: denotes an individual register bit. a[15:0]: denotes a group of similarly named signals, such as address or data bus. a5: denotes one element of a signal group membership, such as an individual address bit. bit: binary unit byte: eight bits word: two bytes, or sixteen bits kbit: 1024 bits kbyte: 1024 bytes kword: 1024 words mbit: 1,048,576 bits mbyte: 1,048,576 bytes mword: 1,048,576 words
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 9 2.0 functional overview this section provides an overview of the features and capabilities of the intel strataflash ? embedded memory (p30) family. the p30 family provides density upgrades from 64-mbit through 512-mbit. this family of devices provides high performance at low voltage on a 16-bit data bus. individually erasable memory blocks are sized for optimum code and data storage. upon initial power up or return from reset, the device defaults to asynchronous page-mode read. configuring the read configuration register enables synchronous burst-mode reads. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. a wait signal provides an easy cpu-to-flash memory synchronization. in addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. designed for low-voltage systems, the intel strataflash ? embedded memory (p30) family supports read operations with v cc at 1.8 v, and erase and program operations with v pp at 1.8 v or 9.0 v. buffered enhanced factory programming (befp) provides the fastest flash array programming performance with v pp at 9.0 v, which increases factory throughput. with v pp at 1.8 v, vcc and vpp can be tied together for a simple, ultra low power design. in addition to voltage flexibility, a dedicated vpp connection provides complete data protection when v pp v pplk . a command user interface (cui) is the interface between the system processor and all internal operations of the device. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and program. a status register indicates erase or program completion and any errors that may have occurred. an industry-standard command sequence invokes program and erase automation. each erase operation erases one block. the erase suspend feature allows system software to pause an erase cycle to read or program data in another block. program suspend allows system software to pause programming to read other locations. data is programmed in word increments (16 bits). the intel strataflash ? embedded memory (p30) family protection register allows unique flash device identification that can be used to increase system security. the individual block lock feature provides zero-latency block locking and unlocking. in addition, the p30 device also has four pre-defined spaces in the main array that can be configured as one-time programmable (otp).
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 10 order number: 306666, revision: 005 3.0 package information 3.1 56-lead tsop package figure 1. tsop mechanical specifications a 0 l detail a y d c z pin 1 e d 1 b detail b see detail a e see detail b a 1 seating plane a 2 see note 2 [231369-90] see notes 1 and 3 table 1. tsop package dimensions (sheet 1 of 2) product information symbol millimeters inches notes min nom max min nom max package height a - - 1.200 - - 0.047 standoff a 1 0.050 - - 0.002 - - package body thickness a 2 0.965 0.995 1.025 0.038 0.039 0.040 lead width b 0.100 0.150 0.200 0.004 0.006 0.008 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 package body length d 1 18.200 18.400 18.600 0.717 0.724 0.732 4 package body width e 13.800 14.000 14.200 0.543 0.551 0.559 4 lead pitch e - 0.500 - - 0.0197 -
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 11 terminal dimension d 19.800 20.00 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 lead count n - 56 - - 56 - lead tip angle ? 0 3 5 0 3 5 seating plane coplanarity y - - 0.100 - - 0.004 lead to package offset z 0.150 0.250 0.350 0.006 0.010 0.014 notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. daisy chain evaluation unit information is at intel? flash memory packaging technology http://developer.intel.com/design/flash/packtech . table 1. tsop package dimensions (sheet 2 of 2) product information symbol millimeters inches notes min nom max min nom max
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 12 order number: 306666, revision: 005 3.2 64-ball easy bga package figure 2. easy bga mechanical specifications table 2. easy bga package dimensions product information symbol millimeters inches notes min nom max min nom max package height (64/128/256-mbit) a - - 1.200 - - 0.0472 package height (512-mbit) a - - 1.300 - - 0.0512 ball height a1 0.250 - - 0.0098 - - package body thickness (64/128/256-mbit) a2 - 0.780 - - 0.0307 - package body thickness (512-mbit) a2 - 0.910 - - 0.0358 - ball (lead) width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976 1 package body length e 12.900 13.000 13.100 0.5079 0.5118 0.5157 1 pitch [e] - 1.000 - - 0.0394 - ball (lead) count n-64- -64- seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 distance along d s1 1.400 1.500 1.600 0.0551 0.0591 0.0630 1 corner to ball a1 distance along e s2 2.900 3.000 3.100 0.1142 0.1181 0.1220 1 notes: 1. daisy chain evaluation unit information is at intel? flash memory packaging technology http://developer.intel.com/design/flash/packtech . e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 87654321 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 13 3.3 quad+ scsp packages figure 3. 64/128-mbit, 88-ball (80 active) quad+ scsp specifications (8x10x1.2 mm) millimeters inches dimensions symbol min nom max min nom max package height a - - 1.200 - - 0.0472 ba ll heig ht a 1 0.200 - - 0.0079 - - package body thickness a 2 - 0.860 - - 0.0339 - ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body length e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e - 0.800 - - 0.0315 - ball (lead) count n - 88 - - 88 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 distance along e s 1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d s 2 0.500 0.600 0.700 0.0197 0.0236 0.0276 top view - ball down bottom view - ball up a a 2 d e y a 1 drawing not to scale. s 2 s 1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m 12345678 a1 index mark
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 14 order number: 306666, revision: 005 figure 4. 256-mbit, 88-ball (80 active) quad+ scsp specifications (8x11x1.0 mm) millimeters inches dimens ions symbol min nom max min nom max package height a - - 1.000 - - 0.0394 ball height a1 0.117 - - 0.0046 - - package body thicknes s a2 - 0.740 - - 0.0291 - ball (lead) width b 0.300 0.350 0.400 0.0118 0.0138 0.0157 package body length d 10.900 11.00 11.100 0.4291 0.4331 0.4370 package body width e 7.900 8.00 8.100 0.3110 0.3150 0.3189 pitch e - 0.80 - - 0.0315 - ball (lead ) cou nt n - 88 - - 88 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 dis tance a long e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 dis tance a long d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 top view - ball down bottom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12 34 56 78 note: dimensions a1, a2, and b are preliminary
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 15 figure 5. 512-mbit, 88-ball (80 active) quad+ scsp specifications (8x11x1.2 mm) millimeters inches dimens ions s ymbol min nom max min nom max package height a - - 1.200 - - 0.0472 ball height a1 0.200 - - 0.0079 - - package body thickness a2 - 0.860 - - 0.0339 - ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 10.900 11.000 11.100 0.4291 0.4331 0.4370 package body w idth e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e - 0.800 - - 0.0315 - ball (lead) count n - 88 - - 88 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 dis tance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 dis tance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12 34 56 78
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 16 order number: 306666, revision: 005 4.0 ballout and signal descriptions 4.1 signal ballout notes: 1. a1 is the least significant address bit. 2. a23 is valid for 128-mbit densities and above; otherwise, it is a no connect (nc). 3. a24 is valid for 256-mbit densities; otherwise, it is a no connect (nc). 4. synchronous burst read operation is currently not supported for the tsop package. the synchronous read input signals (i.e. adv# and clk) should be tied off to support asynchronous reads. see section 4.2, ?signal descriptions? on page 19 . figure 6. 56-lead tsop pinout (64/128/256-mbit) intel strataflash ? embedded memory (p30) 56-lead tsop pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a14 a13 a12 a10 a9 a11 a23 a21 vss a22 vcc wp# a20 we# a19 a8 a7 a18 a6 a4 a3 a5 a2 rfu vss a24 wait dq15 dq7 a17 dq14 dq13 dq5 dq6 dq12 adv# clk dq4 rst# a16 dq3 vpp dq10 vcc q dq9 dq2 dq1 dq0 vcc dq8 oe # ce# a1 vss a15 dq11
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 17 notes: 1. a1 is the least significant address bit. 2. a23 is valid for 128-mbit densities and above; otherwise, it is a no connect (nc). 3. a24 is valid for 256-mbit densities and above; otherwise, it is a no connect (nc). 4. a25 is valid for 512-mbit densities; otherwise, it is a no connect (nc). figure 7. 64-ball easy bga ballout (64/128/256/512-mbit) 1 8 234 5 67 easy bga top view- ball side down easy bga bottom view- ball side up 1 8 2 3 4 5 6 7 h g f e d c b a h g f e d c a a2 vss a9 a14 ce# a19 rfu a25 rfu vss vcc dq13 vss dq7 a24 vss a3 a7 a10 a15 a12 a20 a21 wp# a4 a5 a11 vccq rst# a16 a17 vccq rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe# dq0 dq10 dq12 dq11 wait adv# we# a23 rfu dq2 dq5 vccq dq14 dq6 a1 a6 a8 a13 vpp a18 a22 vcc a23 a4 a5 a11 vccq rst# a16 a17 vccq a1 a6 a8 a13 vpp a18 a22 vcc a3 a7 a10 a15 a12 a20 a21 wp# rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe# dq0 dq10 dq12 dq11 wait adv# we# rfu dq2 dq5 vccq dq14 dq6 a2 vss a9 a14 ce# a19 rfu a25 rfu vss vcc dq13 vss dq7 a24 vss b
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 18 order number: 306666, revision: 005 notes: 1. a22 is valid for 128-mbit densities and above; otherwise, it is a no connect (nc). 2. a23 is valid for 256-mbit densities and above; otherwise, it is a no connect (nc). 3. a24 is valid for 512-mbit densities and above; otherwise, it is a no connect (nc). 4. f2-ce# is a no connect (nc). figure 8. 88-ball (80-active ball) quad+ scsp ballout pin 1 12345678 a du du depop depop depop depop du du a b a4 a18 a19 vss vcc vcc a21 a11 b c a5 rfu a23 vss rfu clk a22 a12 c d a3 a17 a24 vpp rfu rfu a9 a13 d e a2 a7 rfu wp# adv# a20 a10 a15 e f a1 a6 rfu rst# we# a8 a14 a16 f g a0 dq8 dq2 dq10 dq5 dq13 wait f2-ce# g h rfu dq0 dq1 dq3 dq12 dq14 dq7 f2-oe# h j rfu f1-oe# dq9 dq11 dq4 dq6 dq15 vccq j k f1-ce# rfu rfu rfu rfu vcc vccq rfu k l vss vss vccq vcc vss vss vss vss l m du du depop depop depop depop du du m 12345678
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 19 4.2 signal descriptions this section has signal descriptions for the various p30 packages. table 3. tsop and easy bga signal descriptions (sheet 1 of 2) symbol type name and function a[max:1] input address inputs: device address inputs. 64-mbit: a[22:1]; 128-mbit: a[23:1]; 256-mbit: a[24:1]; 512-mbit: a[25:1]. dq[15:0] input/ output data input/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are deasserted. data is internally latched during writes. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. warning: designs not using adv# must tie it to vss to allow addresses to flow through. ce# input flash chip enable: active low input. ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. warning: all chip enables must be high when device is not in use. clk input clock: synchronizes the device with the system?s bus frequency in synchronous-read mode. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. warning: designs not using clk for synchronous read mode must tie it to vccq or vss. oe# input output enable: active low input. oe# low enables the device?s output data buffers during read cycles. oe# high places the data outputs and wait in high-z. rst# input reset: active low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal operation. exit from reset places the device in asynchronous read array mode. wait output wa it: indicates data valid in synchronous array or non-array burst reads. read configuration register bit 10 (rcr[10], wt) determines its polarity when asserted. wait?s active output is v ol or v oh when ce# and oe# are v il . wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous page mode, and all write modes, wait is deasserted. we# input write enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we#. wp# input write protect: active low input. wp# low enables the lock-down mechanism. blocks in lock- down cannot be unlocked with the unlock command. wp# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. vpp power/ input erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl min. v pp must remain above v ppl min to perform in-system flash modification. vpp may be 0 v during read operations. v pph can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 9 v for a cumulative total not to exceed 80 hours. extended use of this pin at 9 v may reduce block cycling capability. vcc power device core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 20 order number: 306666, revision: 005 vccq power output power supply: output-driver source voltage. vss power ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. these should be treated in the same way as a do not use (du) signal. du ? do not use: do not connect to any other signal, or power supply; must be left floating. nc ? no connect: no internal connection; can be driven or floated. table 3. tsop and easy bga signal descriptions (sheet 2 of 2) symbol type name and function table 4. quad+ scsp signal descriptions (sheet 1 of 2) symbol type name and function a[max:0] input address inputs: device address inputs. 64-mbit: a[21:0]; 128-mbit: a[22:0]; 256-mbit: a[23:0]; 512-mbit: a[24:0]. dq[15:0] input/ output data input/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are deasserted. data is internally latched during writes. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. warning: designs not using adv# must tie it to vss to allow addresses to flow through. f1-ce# input flash chip enable: active low input. ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. warning: all chip enables must be high when device is not in use. clk input clock: synchronizes the device with the system?s bus frequency in synchronous-read mode. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. warning: designs not using clk for synchronous read mode must tie it to vccq or vss. f1-oe# f2-oe# input output enable: active low input. oe# low enables the device?s output data buffers during read cycles. oe# high places the data outputs and wait in high-z. f1-oe# and f2-oe# should be tied together for all densities. rst# input reset: active low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal operation. exit from reset places the device in asynchronous read array mode. wait output wait: indicates data valid in synchronous array or non-array burst reads. read configuration register bit 10 (rcr[10], wt) determines its polarity when asserted. wait?s active output is v ol or v oh when ce# and oe# are v il . wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous page mode, and all write modes, wait is deasserted. we# input write enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we#. wp# input write protect: active low input. wp# low enables the lock-down mechanism. blocks in lock- down cannot be unlocked with the unlock command. wp# high overrides the lock-down function enabling blocks to be erased or programmed using software commands.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 21 vpp power/ lnput erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl min. v pp must remain above v ppl min to perform in-system flash modification. vpp may be 0 v during read operations. v pph can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 9 v for a cumulative total not to exceed 80 hours. extended use of this pin at 9 v may reduce block cycling capability. vcc power device core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. vccq power output power supply: output-driver source voltage. vss power ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. these should be treated in the same way as a do not use (du) signal. du ? do not use: do not connect to any other signal, or power supply; must be left floating. nc ? no connect: no internal connection; can be driven or floated. table 4. quad+ scsp signal descriptions (sheet 2 of 2) symbol type name and function
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 22 order number: 306666, revision: 005 4.3 scsp configurations figure 9. 512-mbit easy bga top parameter block diagram figure 10. 512-mbit easy bga bottom parameter block diagram flash die #1 (256-mbit) flash die #2 (256-mbit) wp# clk ce# adv# oe# wait we# rst# vcc vpp dq[15:0 ] a [max:1] vccq vss easy bga 512-mbit (2-die) top parameter configuration flash die #2 (256-mbit) flash die #1 (256-mbit) wp# clk ce# adv# oe# wait we# rst# vcc vpp dq[15:0 ] a [max:1] vccq vss easy bga 512-mbit (2-die) bottom parameter configuration
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 23 figure 11. 512-mbit quad+ scsp top parameter block diagram figure 12. 512-mbit quad+ scsp bottom parameter block diagram flash die #1 (256-mbit) flash die #2 (256-mbit) wp# clk f1-ce# adv# oe# wait we# rst# vcc vpp dq[15:0 ] a [max:0] vccq vss quad+ 512-mbit (2-die) top parameter configuration flash die #2 (256-mbit) flash die #1 (256-mbit) wp# clk f1-ce# adv# oe# wait we# rst# vcc vpp dq[15:0 ] a [max:0] vccq vss quad+ 512-mbit (2-die) bottom parameter configuration
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 24 order number: 306666, revision: 005 4.4 memory maps table 5 through table 8 show the p30 memory maps. the memory array is divided into multiple 8- mbit programming regions (see section 11.0, ?programming operations? on page 60 ). table 5. discrete top parameter memory maps (all packages) size (kb) blk 64-mbit size (kb) blk 128-mbit one programming region 32 66 3fc000 - 3fffff one programming region 32 130 7fc000 - 7fffff ... ... ... ... ... ... 32 63 3f0000 - 3f3fff 32 127 7f0000 - 7f3fff 128 62 3e0000 - 3effff 128 126 7e0000 - 7effff ... ... ... ... ... ... 128 56 380000 - 38ffff 128 120 780000 - 78ffff seven programming regions 128 55 370000 - 37ffff fifteen programming regions 128 119 770000 - 77ffff 128 54 360000 - 36ffff 128 118 760000 - 76ffff ... ... ... ... ... ... 128 1 010000 - 01ffff 128 1 010000 - 01ffff 128 0 000000 - 00ffff 128 0 000000 - 00ffff size (kb) blk 256-mbit one programming region 32 258 ffc000 - ffffff ... ... ... 32 255 ff0000 - ff3fff 128 254 fe0000 - feffff ... ... ... 128 248 f80000 - f8ffff thirty-one programming regions 128 247 f70000 - f7ffff 128 246 f60000 - f6ffff ... ... ... 128 1 010000 - 01ffff 128 0 000000 - 00ffff
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 25 table 6. discrete bottom parameter memory maps (all packages) size (kb) blk 64-mbit size (kb) blk 128-mbit seven programming regions 128 66 3f0000 - 3fffff fifteen programming regions 128 130 7f0000 - 7fffff 128 65 3e0000 - 3effff 128 129 7e0000 - 7effff ... ... ... ... ... ... 128 12 090000 - 09ffff 128 12 090000 - 09ffff 128 11 080000 - 08ffff 128 11 080000 - 08ffff one programming region 128 10 070000 - 07ffff one programming region 128 10 070000 - 07ffff ... ... ... ... ... ... 128 4 010000 - 01ffff 128 4 010000 - 01ffff 32 3 00c000 - 00ffff 32 3 00c000 - 00ffff ... ... ... ... ... ... 32 0 000000 - 003fff 32 0 000000 - 003fff size (kb) blk 256-mbit thirty-one programming regions 128 258 ff0000 - ffffff 128 257 fe0000 - feffff ... ... ... 128 12 090000 - 09ffff 128 11 080000 - 08ffff one programming region 128 10 070000 - 07ffff ... ... ... 128 4 010000 - 01ffff 32 3 00c000 - 00ffff ... ... ... 32 0 000000 - 003fff
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 26 order number: 306666, revision: 005 note: the stacked p30 memory maps are the same for both parameter options because the devices employ virtual chip enable. the parameter option only defines the placement of die #1. table 7. 512-mbit top parameter memory map (easy bga and quad+ scsp) flash die # die stack config. size (kb) 512-mbit flash (2x256-mbit w/ 1ce) blk address range 1 flash die #1 (top parameter) 32 258 ffc000 - ffffff ... ... ... 32 255 ff0000 - ff3fff 128 254 fe0000 - feffff ... ... ... 128 0 000000 - 00ffff 2 flash die #2 (bottom parameter) 128 258 ff0000 - ffffff ... ... ... 128 4 010000 - 01ffff 32 3 00c000 - 00ffff ... ... ... 32 0 000000 - 003fff note: refer to 256-mbit memory map ( table 5 and table 6 ) for programming region information. table 8. 512-mbit bottom parameter memory map (easy bga and quad+ scsp) flash die # die stack config. size (kb) 512-mbit flash (2x256-mbit w/ 1ce) blk address range 2 flash die #2 (top parameter) 32 258 ffc000 - ffffff ... ... ... 32 255 ff0000 - ff3fff 128 254 fe0000 - feffff ... ... ... 128 0 000000 - 00ffff 1 flash die #1 (bottom parameter) 128 258 ff0000 - ffffff ... ... ... 128 4 010000 - 01ffff 32 3 00c000 - 00ffff ... ... ... 32 0 000000 - 003fff note: refer to 256-mbit memory map ( table 5 and table 6 ) for programming region information.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 27 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. parameter maximum rating notes temperature under bias 64mb ? 512mb ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any signal (except vcc, vpp) ?0.5 v to +4.1 v 1 vpp voltage ?0.2 v to +10 v 1,2,3 vcc voltage ?0.2 v to +2.5 v 1 vccq voltage ?0.2 v to +4.1 v 1 output short circuit current 100 ma 4 notes: 1. voltages shown are specified with respect to v ss . minimum dc voltage is ?0.5 v on input/output signals and ?0.2 v on v cc , v ccq , and v pp . during transitions, this level may undershoot to ?2.0 v for periods less than 20 ns. maximum dc voltage on v cc is v cc + 0.5 v, which, during transitions, may overshoot to v cc + 2.0 v for periods less than 20 ns. maximum dc voltage on input/output signals and v ccq is v ccq + 0.5 v, which, during transitions, may overshoot to v ccq + 2.0 v for periods less than 20 ns. 2. maximum dc voltage on v pp may overshoot to +11.5 v for periods less than 20 ns. 3. program/erase voltage is typically 1.7 v ? 2.0 v. 9.0 v can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 v program/erase voltage may reduce block cycling capability. 4. output shorted for no more than one second. no more than one output shorted at a time.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 28 order number: 306666, revision: 005 5.2 operating conditions note: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 9. operating conditions symbol parameter min max units notes t c operating temperature 64mb ? 512mb ?40 +85 c 1 v cc vcc supply voltage 1.7 2.0 v v ccq i/o supply voltage cmos inputs 1.7 3.6 ttl inputs 2.4 3.6 v ppl v pp voltage supply (logic level) 0.9 3.6 2 v pph factory word programming v pp 8.5 9.5 t pph maximum vpp hours v pp = v pph -80hours block erase cycles main and parameter blocks v pp = v ppl 100,000 - cycles main blocks v pp = v pph -1000 parameter blocks v pp = v pph -2500 notes: 1. t c = case temperature. 2. in typical operation vpp program voltage is v ppl .
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 29 6.0 electrical specifications 6.1 dc current characteristics table 10. dc current characteristics (sheet 1 of 2) sym parameter cmos inputs (v ccq = 1.7 v - 3.6 v) ttl inputs (v ccq = 2.4 v - 3.6 v) unit test conditions notes typ max typ max i li input load current - 1 - 2 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current dq[15:0], wait - 1 - 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss i ccs , i ccd v cc standby, power down 64-mbit 20 35 20 35 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq (for i ccs ) rst# = v ss (for i ccd ) wp# = v ih 1,2 128-mbit 30 75 30 75 256-mbit 55 115 55 200 512-mbit 110 230 110 400 i ccr average v cc read current asynchronous single- word f = 5 mhz (1 clk) 14 16 14 16 ma 1-word read v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1 page-mode read f = 13 mhz (5 clk) 910910ma 4-word read synchronous burst f = 40 mhz 13 17 n/a n/a ma bl = 4w 15 19 n/a n/a ma bl = 8w 17 21 n/a n/a ma bl = 16w 21 26 n/a n/a ma bl = cont. i ccw, i cce v cc program current, v cc erase current 36 51 36 51 ma v pp = v ppl , pgm/ers in progress 1,3,5 26 33 26 33 v pp = v pph , pgm/ers in progress 1,3,5 i ccws, i cces v cc program suspend current, v cc erase suspend current 64-mbit 20 35 20 35 a ce# = v ccq ; suspend in progress 1,3,4 128-mbit 30 75 30 75 256-mbit 55 115 55 200 512-mbit 110 230 110 400 i pps, i ppws, i ppes v pp standby current, v pp program suspend current, v pp erase suspend current 0.2 5 0.2 5 a v pp = v ppl , suspend in progress 1,3 i ppr v pp read 2 15 2 15 a v pp = v ppl 1,3 i ppw v pp program current 0.05 0.10 0.05 0.10 ma v pp = v ppl, program in progress 822822 v pp = v pph, program in progress
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 30 order number: 306666, revision: 005 i ppe v pp erase current 0.05 0.10 0.05 0.10 ma v pp = v ppl, erase in progress 822822 v pp = v pph, erase in progress notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25 c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after ce# is deasserted. 3. sampled, not 100% tested. 4. i cces is specified with the device deselected. if device is read while in erase suspend, current is i cces plus i ccr . 5. i ccw , i cce measured over typical or max times specified in section 7.5, ?program and erase characteristics? on page 44 . table 10. dc current characteristics (sheet 2 of 2) sym parameter cmos inputs (v ccq = 1.7 v - 3.6 v) ttl inputs (v ccq = 2.4 v - 3.6 v) unit test conditions notes typ max typ max
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 31 6.2 dc voltage characteristics table 11. dc voltage characteristics sym parameter cmos inputs (v ccq = 1.7 v ? 3.6 v) ttl inputs (1) (v ccq = 2.4 v ? 3.6 v) unit test condition notes min max min max v il input low voltage 0 0.4 0 0.6 v 2 v ih input high voltage v ccq ? 0.4 v v ccq 2.0 v ccq v v ol output low voltage - 0.1 - 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ? 0.1 - v ccq ? 0.1 - v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock-out voltage - 0.4 - 0.4 v 3 v lko v cc lock voltage 1.0 - 1.0 - v v lkoq v ccq lock voltage 0.9 - 0.9 - v notes: 1. synchronous read mode is not supported with ttl inputs. 2. v il can undershoot to ?0.4 v and v ih can overshoot to v ccq + 0.4 v for durations of 20 ns or less. 3. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 32 order number: 306666, revision: 005 7.0 ac characteristics 7.1 ac test conditions note: ac test inputs are driven at v ccq for logic "1" and 0 v for logic "0." input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at v cc = v cc min. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance . figure 13. ac input/output reference waveform io_ref.w mf input v ccq /2 v ccq /2 output v ccq 0v test points figure 14. transient equivalent testing load circuit device under test ou t c l table 12. test configuration component value for worst case speed conditions test configuration c l (pf) v ccq min standard test 30 figure 15. clock input ac waveform clk [c] v ih v il r203 r202 r201
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 33 7.2 capacitance table 13. capacitance symbol parameter signals min typ max unit condition note c in input capacitance address, data, ce#, we#, oe#, rst#, clk, adv#, wp# 26 7 pf typ temp = 25 c, max temp = 85 c, v cc = (0 v - 2.0 v), v ccq = (0 v - 3.6 v), discrete silicon die 1,2,3 c out output capacitance data, wait 2 4 5 pf notes: 1. capacitance values are for a single die; for 2-die and 4-die stacks multiply the capacitance values by the number of die in the stack. 2. sampled, not 100% tested. 3. silicon die capacitance only, add 1 pf for discrete packages.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 34 order number: 306666, revision: 005 7.3 ac read specifications table 14. ac read specifications for 64/128-mbit densities (sheet 1 of 2) num symbol parameter min max unit notes asynchronous specifications r1 t avav read cycle time 85 - ns r2 t avqv address to output valid - 85 ns r3 t elqv ce# low to output valid - 85 ns r4 t glqv oe# low to output valid - 25 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 24 ns 1,3 r9 t ghqz oe# high to output in high-z - 24 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 - ns r11 t ehel ce# pulse width high 20 - ns 1 r12 t eltv ce# low to wait valid - 17 ns r13 t ehtz ce# high to wait high-z - 20 ns 1,3 r15 t gltv oe# low to wait valid - 17 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 20 ns latching specifications r101 t avv h address setup to adv# high 10 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid - 85 ns r104 t vlvh adv# pulse width low 10 - ns r105 t vhvl adv# pulse width high 10 - ns r106 t vhax address hold from adv# high 9 - ns 1,4 r108 t apa page address access - 25 ns 1 r111 t phvh rst# high to adv# high 30 - ns clock specifications r200 f clk clk frequency - 40 mhz 1,3,5,6 r201 t clk clk period 25 - ns r202 t ch/cl clk high/low time 5 - ns r203 t fclk/rclk clk fall/rise time - 3 ns synchronous specifications (5,6) r301 t avch/l address setup to clk 9 - ns 1 r302 t vlch/l adv# low setup to clk 9 - ns r303 t elch/l ce# low setup to clk 9 - ns r304 t chqv / t clqv clk to output valid - 20 ns
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 35 r305 t chqx output hold from clk 3 - ns 1,7 r306 t chax address hold from clk 10 - ns 1,4,7 r307 t chtv clk to wait valid - 20 ns 1,7 r311 t chvl clk valid to adv# setup 3 - ns 1 r312 t chtx wait hold from clk 3 - ns 1,7 notes: 1. see figure 13, ?ac input/output reference waveform? on page 32 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv . 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. synchronous burst read operation is currently not supported for the tsop package. 6. synchronous read mode is not supported with ttl level inputs. 7. applies only to subsequent synchronous reads. table 15. ac read specifications for 256/512-mbit densities (sheet 1 of 2) num symbol parameter speed min max unit notes asynchronous specifications r1 t avav read cycle time v cc = 1.8 v ? 2.0 v 85 - ns v cc = 1.7 v ? 2.0 v 88 - 256m tsop package 95 r2 t av qv address to output valid v cc = 1.8 v ? 2.0 v -85 ns v cc = 1.7 v ? 2.0 v -88 256m tsop package - 95 r3 t elqv ce# low to output valid v cc = 1.8 v ? 2.0 v -85 ns v cc = 1.7 v ? 2.0 v -88 256m tsop package - 95 r4 t glqv oe# low to output valid - 25 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 24 ns 1,3 r9 t ghqz oe# high to output in high-z - 24 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 - ns r11 t ehel ce# pulse width high 20 - ns 1 r12 t eltv ce# low to wait valid - 17 ns r13 t ehtz ce# high to wait high-z - 20 ns 1,3 r15 t gltv oe# low to wait valid - 17 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 20 ns latching specifications table 14. ac read specifications for 64/128-mbit densities (sheet 2 of 2) num symbol parameter min max unit notes
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 36 order number: 306666, revision: 005 r101 t avv h address setup to adv# high 10 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid v cc = 1.8 v ? 2.0 v -85 ns v cc = 1.7 v ? 2.0 v -88 256m tsop package - 95 r104 t vlvh adv# pulse width low 10 - ns r105 t vhvl adv# pulse width high 10 - ns r106 t vhax address hold from adv# high 9 - ns 1,4 r108 t apa page address access - 25 ns 1 r111 t phvh rst# high to adv# high 30 - ns clock specifications r200 f clk clk frequency - 40 mhz 1,3,5,6 r201 t clk clk period 25 - ns r202 t ch/cl clk high/low time 5 - ns r203 t fclk/rclk clk fall/rise time - 3 ns synchronous specifications (5,6) r301 t avch/l address setup to clk 9 - ns 1 r302 t vlch/l adv# low setup to clk 9 - ns r303 t elch/l ce# low setup to clk 9 - ns r304 t chqv / t clqv clk to output valid - 20 ns r305 t chqx output hold from clk 3 - ns 1,7 r306 t chax address hold from clk 10 - ns 1,4,7 r307 t chtv clk to wait valid - 20 ns 1,7 r311 t chvl clk valid to adv# setup 3 - ns 1 r312 t chtx wait hold from clk 3 - ns 1,7 notes: 1. see figure 13, ?ac input/output reference waveform? on page 32 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv . 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. synchronous burst read operation is currently not supported for the tsop package. 6. synchronous read mode is not supported with ttl level inputs. 7. applies only to subsequent synchronous reads. table 15. ac read specifications for 256/512-mbit densities (sheet 2 of 2) num symbol parameter speed min max unit notes
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 37 note: wait shown deasserted during asynchronous read mode (rcr[10]=0, wait asserted low). note: wait shown deasserted during asynchronous read mode (rcr[10]=0, wait asserted low). figure 16. asynchronous single-word read (adv# low) r5 r7 r6 r17 r15 r9 r4 r8 r3 r1 r2 r1 a ddress [a] adv# ce# [e} oe# [g] wait [t] data [d/q] rst# [p] figure 17. asynchronous single-word read (adv# latch) r10 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 a ddress [a] a[1:0][a] adv# ce# [e} oe# [g] wait [t] data [d/q]
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 38 order number: 306666, revision: 005 note: wait shown deasserted during asynchronous read mode (rcr[10]=0, wait asserted low). 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. this diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by ce# deassertion after the first word in the burst. figure 18. asynchronous page-mode read timing r108 r9 r7 r17 r15 r10 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 a [max:2] [a] a[1:0] adv# ce# [e] oe# [g] wait [t] data [d/q] figure 19. synchronous single-word array or non-array read timing r312 r305 r304 r4 r17 r307 r15 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a d d re ss [ a ] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 39 notes: 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. at the end of word line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. note: wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (rcr[10] = 0, wait asserted low). figure 20. continuous burst read, showing an output delay timing r305 r3 05 r3 05 r305 r304 r4 r7 r3 12 r307 r15 r30 3 r102 r3 r106 r105 r105 r101 r2 r304 r3 04 r3 04 r3 06 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 21. synchronous burst-mode four-word read timing latency count a q0 q1 q2 q3 r307 r10 r304 r305 r304 r4 r7 r17 r15 r9 r8 r303 r3 r106 r102 r105 r105 r101 r2 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 40 order number: 306666, revision: 005 7.4 ac write specifications table 16. ac write specifications num symbol parameter min max units notes w1 t phwl rst# high recovery to we# low 150 - ns 1,2,3 w2 t elwl ce# setup to we# low 0 - ns 1,2,3 w3 t wlwh we# write pulse width low 50 - ns 1,2,4 w4 t dvwh data setup to we# high 50 - ns 1,2 w5 t avwh address setup to we# high 50 - ns w6 t wheh ce# hold from we# high 0 - ns w7 t whdx data hold from we# high 0 - ns w8 t whax address hold from we# high 0 - ns w9 t whwl we# pulse width high 20 - ns 1,2,5 w10 t vpwh v pp setup to we# high 200 - ns 1,2,3,7 w11 t qvvl v pp hold from status read 0 - ns w12 t qvbl wp# hold from status read 0 - ns 1,2,3,7 w13 t bhwh wp# setup to we# high 200 - ns w14 t whgl we# high to oe# low 0 - ns 1,2,9 w16 t whqv we# high to read valid t avqv + 35 - ns 1,2,3,6,10 write to asynchronous read specifications w18 t whav we# high to address valid 0 - ns 1,2,3,6,8 write to synchronous read specifications w19 t whch/l we# high to clock valid 19 - ns 1,2,3,6,10 w20 t whvh we# high to adv# high 19 - ns write specifications with clock active w21 t vhwl adv# high to we# low - 20 ns 1,2,3,11 w22 t chwl clock high to we# low - 20 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchronous burst read. 7. v pp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asynchronous read. see spec w19 and w20 for synchronous read. 9. when doing a read status operation following any command that alters the status register, w14 is 20 ns. 10. add 10 ns if the write operation results in a rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 41 note: wait deasserted during asynchronous read and during write. wait high-z during write per oe# deasserted. figure 22. write-to-write timing w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a ddress [a] ce# [e} we# [ w] oe# [g] data [d/q] rst# [p] figure 23. asynchronous read-to-write timing q d r5 w7 w4 r10 r7 r6 r17 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e} oe# [g] we# [w] wait [t] data [d/q] rst # [p]
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 42 order number: 306666, revision: 005 note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr[10]=0, wait asserted low). clock is ignored during write operation. figure 24. write-to-asynchronous read timing d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w1 4 w1 8 w3 w3 r10 w6 w2 r1 r1 w8 w5 a ddress [a] adv# [v] ce# [e} we # [w] oe# [g] wait [t] data [d/q] rst # [p] figure 25. synchronous read-to-write timing latency count q d d w7 r305 r304 r7 r312 r307 r16 w15 w22 w21 w9 w8 w9 w3 w22 w21 w3 w2 r8 r4 w6 r11 r13 r11 r303 r3 r104 r104 r106 r102 r105 r105 w18 w5 r101 r2 r 306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] we# wait [t] data [d/q]
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 43 note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr[10]=0, wait asserted low). figure 26. write-to-synchronous read timing d q q w1 r304 r305 r304 r3 w7 w4 r307 r15 r4 w20 w19 w18 w3 w3 r11 r303 r11 w6 w2 r104 r106 r104 r306 w8 w5 r302 r 301 r2 clk a ddress [a] adv# ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p]
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 44 order number: 306666, revision: 005 7.5 program and erase characteristics num symbol parameter v ppl v pph units notes min typ max min typ max conventional word programming w200 t prog/w program time single word -90200-85190 s 1 single cell - 30 60 - 30 60 buffered programming w200 t prog/w program time single word -90200-85190 s 1 w251 t buff 32-word buffer - 440 880 - 340 680 buffered enhanced factory programming w451 t befp/w program single word n/a n/a n/a - 10 - s 1,2 w452 t befp/ setup befp setup n/a n/a n/a 5 - - 1 erasing and suspending w500 t ers/pb erase time 32-kbyte parameter - 0.4 2.5 - 0.4 2.5 s 1 w501 t ers/mb 128-kbyte main - 1.2 4.0 - 1.0 4.0 w600 t susp/p suspend latency program suspend - 20 25 - 20 25 s w601 t susp/e erase suspend - 20 25 - 20 25 notes: 1. typical values measured at t c = +25 c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. averaged over entire device.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 45 8.0 power and reset specifications 8.1 power up and down power supply sequencing is not required if vpp is connected to vcc or vccq. otherwise v cc and v ccq should attain their minimum operating voltage before applying v pp . power supply transitions should only occur when rst# is low. this protects the device from accidental programming or erasure during power transitions. 8.2 reset specifications asserting rst# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization may not occur. this is because the flash memory may be providing status information, instead of array data as expected. connect rst# to the same active low reset signal used for cpu initialization. also, because the device is disabled when rst# is asserted, it ignores its control inputs during power-up/down. invalid bus conditions are masked, providing a level of memory protection. num symbol parameter min max unit notes p1 t plph rst# pulse width low 100 - ns 1,2,3,4 p2 t plrh rst# low to device reset during erase - 25 s 1,3,4,7 rst# low to device reset during program - 25 1,3,4,7 p3 t vccph v cc power valid to rst# de-assertion (high) 60 - 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to vcc. 4. sampled, but not 100% tested. 5. if rst# is tied to the v cc supply, device will not be ready until t vccph after v cc v ccmin . 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v ccmin . 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 46 order number: 306666, revision: 005 8.3 power supply decoupling flash memory devices require careful power supply de-coupling. three basic power supply current considerations are 1) standby current levels, 2) active current levels, and 3) transient peaks produced when ce# and oe# are asserted and deasserted. when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal logic states change at high speed. all of these internal activities produce transient signals. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. because intel ? multi-level cell (mlc) flash memory devices draw their power from v cc , vpp, and vccq, each power connection should have a 0.1 f ceramic capacitor to ground. high- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. figure 27. reset operation waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 47 9.0 device operations this section provides an overview of device operations. the system cpu provides control of all in- system read, write, and erase operations of the device via the system bus. the on-chip write state machine (wsm) manages all block-erase and word-program algorithms. device commands are written to the command user interface (cui) to control all flash memory device operations. the cui does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 bus operations ce# low and rst# high enable device read operations. the device internally decodes upper address inputs to determine the accessed block. adv# low opens the internal address latches. oe# low activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low. in synchronous mode, the address is latched by the first of either the rising adv# edge or the next valid clk edge with adv# low (we# and rst# must be v ih ; ce# must be v il ). bus cycles to/from the p30 device conform to standard microprocessor bus operations. table 17 summarizes the bus operations and the logic levels that must be applied to the device control signal inputs. 9.1.1 reads to perform a read operation, rst# and we# must be deasserted while ce# and oe# are asserted. ce# is the device-select control. when asserted, it enables the flash memory device. oe# is the data-output control. when asserted, the addressed flash memory data is driven onto the i/o bus. see section 10.0, ?read operations? on page 52 for details on the available read modes, and see section 14.0, ?special read states? on page 73 for details regarding the available read states. table 17. bus operations summary bus operation rst# clk adv# ce# oe# we# wait dq[15:0] notes read asynchronous v ih x l l l h deasserted output synchronous v ih running l l l h driven output write v ih x l l h l high-z input 1 output disable v ih x x l h h high-z high-z 2 standby v ih x x h x x high-z high-z 2 reset v il x x x x x high-z high-z 2,3 notes: 1. refer to the table 18, ?command bus cycles? on page 49 for valid dq[15:0] during a write operation. 2. x = don?t care (h or l). 3. rst# must be at v ss 0.2 v to meet the maximum specified power-down current.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 48 order number: 306666, revision: 005 9.1.2 writes to perform a write operation, both ce# and we# are asserted while rst# and oe# are deasserted. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. table 18, ?command bus cycles? on page 49 shows the bus cycle sequence for each of the supported device commands, while table 19, ?command codes and definitions? on page 50 describes each command. see section 7.0, ?ac characteristics? on page 32 for signal-timing details. note: write operations with invalid v cc and/or v pp voltages can produce spurious results and should not be attempted. 9.1.3 output disable when oe# is deasserted, device outputs dq[15:0] are disabled and placed in a high - impedance (high-z) state, wait is also placed in high-z. 9.1.4 standby when ce# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, independent of the level placed on oe#. standby current, i ccs , is the average current measured over any 5 ms time interval, 5 s after ce# is deasserted. during standby, average current is measured over the same time interval 5 s after ce# is deasserted. when the device is deselected (while ce# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 9.1.5 reset as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. if a cpu reset occurs with no flash memory reset, improper cpu initialization may occur because the flash memory may be providing status information rather than array data. flash memory devices from intel allow proper cpu initialization following a system reset through the use of the rst# input. rst# should be controlled by the same low-true reset signal that resets the system cpu. after initial power-up or reset, the device defaults to asynchronous read array, and the status register is set to 0x80. asserting rst# de-energizes all internal circuits, and places the output drivers in high-z. when rst# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. when rst# has been deasserted, the device is reset to asynchronous read array state. note: if rst# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. when returning from a reset (rst# deasserted), a minimum wait is required before the initial read access outputs valid data. also, a minimum delay is required after a reset before a write cycle can be initiated. after this wake - up interval passes, normal operation is restored. see section 7.0, ?ac characteristics? on page 32 for details about signal-timing.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 49 9.2 device commands device operations are initiated by writing specific device commands to the command user interface (cui). see table 18, ?command bus cycles? on page 49 . several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally - timed functions that culminate in the completion of the requested task. however, the operation can be aborted by either asserting rst# or by issuing an appropriate suspend command. table 18. command bus cycles (sheet 1 of 2) mode command bus cycles first bus cycle second bus cycle oper addr (1) data (2) oper addr (1) data (2) read read array 1 write dba 0xff - - - read device identifier 2 write dba 0x90 read dba + ia id cfi query 2 write dba 0x98 read dba + qa qd read status register 2 write dba 0x70 read dba srd clear status register 1 write dba 0x50 - - - program word program 2 write wa 0x40/ 0x10 write wa wd buffered program (3) > 2 write wa 0xe8 write wa n - 1 buffered enhanced factory program (befp) (4) > 2writewa0x80write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write dba 0xb0 - - - program/erase resume 1 write dba 0xd0 - - - block locking/ unlocking lock block 2 write ba 0x60 write ba 0x01 unlock block 2 write ba 0x60 write ba 0xd0 lock-down block 2 write ba 0x60 write ba 0x2f
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 50 order number: 306666, revision: 005 9.3 command definitions valid device command codes and descriptions are shown in table 19 . protection program protection register 2 write pra 0xc0 write pra pd program lock register 2 write lra 0xc0 write lra lrd configuration program read configuration register 2 write rcd 0x60 write rcd 0x03 notes: 1. first command cycle address should be the same as the operation?s target address. dba = device base address (note: needed for 2 or more die stacks) ia = identification code address offset. qa = cfi query address offset. wa = word address of memory location to be written. ba = address within the block. pra = protection register address. lra = lock register address. rcd = read configuration register data on a[15:0]. 2. id = identifier data. qd = query data on dq[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. pd = protection register data. lrd = lock register data. 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 32 words of data.then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data. table 18. command bus cycles (sheet 2 of 2) mode command bus cycles first bus cycle second bus cycle oper addr (1) data (2) oper addr (1) data (2) table 19. command codes and definitions (sheet 1 of 2) mode code device mode description read 0xff read array places the device in read array mode. array data is output on dq[15:0]. 0x70 read status register places the device in read status register mode. the device enters this mode after a program or erase command is issued. status register data is output on dq[7:0]. 0x90 read device id or configuration register places device in read device identifier mode. subsequent reads output manufacturer/device codes, configuration register data, block lock status, or protection register data on dq[15:0]. 0x98 read query places the device in read query mode. subsequent reads output common flash interface information on dq[7:0]. 0x50 clear status register the wsm can only set status register error bits. the clear status register command is used to clear the sr error bits. write 0x40 word program setup first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorithm at the addressed location. during program operations, the device responds only to read status register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array reads. the read array command must be issued to read array data after programming has finished.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 51 write 0x10 alternate word program setup equivalent to the word program setup command, 0x40. 0xe8 buffered program this command loads a variable number of words up to the buffer size of 32 words onto the program buffer. 0xd0 buffered program confirm the confirm command is issued after the data streaming for writing into the buffer is done. this instructs the wsm to perform the buffered program algorithm, writing the data from the buffer to the flash memory array. 0x80 befp setup first cycle of a 2-cycle command; initiates buffered enhanced factory program mode (befp). the cui then waits for the befp confirm command, 0xd0, that initiates the befp algorithm. all other commands are ignored when befp mode begins. 0xd0 befp confirm if the previous command was befp setup (0x80), the cui latches the address and data, and prepares the device for befp mode. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. if the next command is not the erase confirm (0xd0) command, the cui sets status register bits sr[4] and sr[5], and places the device in read status register mode. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block- erase operations, the device responds only to read status register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array reads suspend 0xb0 program or erase suspend this command issued to any device address initiates a suspend of the currently-executing program or block erase operation. the status register indicates successful suspend operation by setting either sr[2] (program suspended) or sr[6] (erase suspended), along with sr[7] (ready). the write state machine remains in the suspend mode regardless of control signal states (except for rst# asserted). 0xd0 suspend resume this command issued to any device address resumes the suspended program or block-erase operation. block locking/ unlocking 0x60 lock block setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock-down (0x2f), the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x01 lock block if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 unlock block if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock-down state, the operation has no effect. 0x2f lock-down block if the previous command was block lock setup (0x60), the addressed block is locked down. protection 0xc0 program protection register setup first cycle of a 2-cycle command; prepares the device for a protection register or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm configuration 0x60 read configuration register setup first cycle of a 2-cycle command; prepares the cui for device read configuration. if the set read configuration register command (0x03) is not the next command, the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x03 read configuration register if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[15:0] to the read configuration register. following a configure read configuration register command, subsequent read operations access array data. table 19. command codes and definitions (sheet 2 of 2) mode code device mode description
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 52 order number: 306666, revision: 005 10.0 read operations the device supports two read modes: asynchronous page mode and synchronous burst mode. asynchronous page mode is the default read mode after device power-up or a reset. the read configuration register must be configured to enable synchronous burst reads of the flash memory array (see section 10.3, ?read configuration register? on page 53 ). the device can be in any of four read states: read array, read identifier, read status or read query. upon power-up, or after a reset, the device defaults to read array. to change the read state, the appropriate read command must be written to the device (see section 9.2, ?device commands? on page 49 ). see section 14.0, ?special read states? on page 73 for details regarding read status, read id, and cfi query modes. the following sections describe read-mode operations in detail. 10.1 asynchronous page-mode read following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to read array. however, to perform array reads after any other device operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. note: asynchronous page-mode reads can only be performed when read configuration register bit rcr[15] is set (see section 10.3, ?read configuration register? on page 53 ). to perform an asynchronous page-mode read, an address is driven onto the address bus, and ce# and adv# are asserted. we# and rst# must already have been deasserted. wait is deasserted during asynchronous page mode. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. clk is not used for asynchronous page-mode reads, and is ignored. if only asynchronous reads are to be performed, clk should be tied to a valid v ih level, wait signal can be floated and adv# must be tied to ground. array data is driven onto dq[15:0] after an initial access time t avqv delay. (see section 7.0, ?ac characteristics? on page 32 ). in asynchronous page mode, four data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on the address bus is driven onto dq[15:0] after the initial access delay. the lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time. 10.2 synchronous burst-mode read to perform a synchronous burst- read, an initial address is driven onto the address bus, and ce# and adv# are asserted. we# and rst# must already have been deasserted. adv# is asserted, and then deasserted to latch the address. alternately, adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid clk edge while adv# is asserted. during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid clk edge after the initial access latency delay (see section 10.3.2, ?latency count? on page 54 ). subsequent data is output on valid clk edges following a minimum delay.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 53 however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. refer to the following waveforms for more detailed information: ? figure 19, ?synchronous single-word array or non-array read timing? on page 38 ? figure 20, ?continuous burst read, showing an output delay timing? on page 39 ? figure 21, ?synchronous burst-mode four-word read timing? on page 39 10.3 read configuration register the read configuration register (rcr) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. to modify rcr settings, use the configure read configuration register command (see section 9.2, ?device commands? on page 49 ). rcr contents can be examined using the read device identifier command, and then reading from offset 0x05 (see section 14.2, ?read device identifier? on page 74 ). the rcr is shown in table 20 . the following sections describe each rcr bit. table 20. read configuration register description (sheet 1 of 2) read configuration register (rcr) read mode res latency count wait polarity data hold wait delay burst seq clk edge res res burst wrap burst length rm r lc[2:0] wp dh wd bs ce r r bw bl[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default) 14 reserved (r) reserved bits should be cleared (0) 13:11 latency count (lc[2:0]) 010 =code 2 011 =code 3 100 =code 4 101 =code 5 110 =code 6 111 =code 7 (default) (other bit settings are reserved) 10 wait polarity (wp) 0 = wait signal is active low 1 = wait signal is active high (default) 9 data hold (dh) 0 = data held for a 1-clock data cycle 1 = data held for a 2-clock data cycle (default) 8 wait delay (wd) 0 = wait deasserted with valid data 1 =wait deasserted one data cycle before valid data (default) 7 burst sequence (bs) 0 = reserved 1 = linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) reserved bits should be cleared (0)
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 54 order number: 306666, revision: 005 10.3.1 read mode the read mode (rm) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. 10.3.2 latency count the latency count bits, lc[2:0], tell the device how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first data word is to be driven onto dq[15:0]. the input clock frequency is used to determine this value. figure 28 shows the data output latency for the different settings of lc[2:0]. synchronous burst at 40 mhz with a latency count setting of code 3 will result in zero wait states; however, a latency count setting of code 4 will cause 1 wait state (code 5 will cause 2 wait states, and so on) after every four words, regardless of whether a 16-word boundary is crossed. if rcr[9] (data hold) bit is set (data hold of two clocks) this wait condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent wait states. refer to table 21, ?lc and frequency support? on page 55 for latency code settings. 3 burst wrap (bw) 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =continuous-word burst (default) (other bit settings are reserved) note: latency code 2, data hold for a 2-clock data cycle (dh = 1) wait must be deasserted with valid data (wd = 0). latency code 2, data hold for a 2-cock data cycle (dh=1) wait deasserted one data cycle before valid data (wd = 1) combination is not supported. table 20. read configuration register description (sheet 2 of 2)
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 55 figure 28. first-access latency count code 1 (reserved code 6 code 5 code 4 code 3 code 2 code 0 (reserved) code 7 valid address valid output valid output valid output valid output valid output valid output valid output vali d out put valid output valid output valid output valid output valid output valid output vali d out put valid output valid output valid output valid output valid output vali d out put valid output valid output valid output valid output vali d out put valid output valid output valid output vali d out put valid output valid output vali d out put valid output vali d out put vali d out put address [a] adv# [v] d q 15-0 [d/q] clk [c] d q 15-0 [d/q] d q 15-0 [d/q] d q 15-0 [d/q] d q 15-0 [d/q] d q 15-0 [d/q] d q 15-0 [d/q] d q 15-0 [d/q] table 21. lc and frequency support latency count settings frequency support (mhz) 2 27 3 40 note: synchronous burst read operation is currently not supported for the tsop package.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 56 order number: 306666, revision: 005 10.3.3 wait polarity the wait polarity bit (wp), rcr[10] determines the asserted level (v oh or v ol ) of wait. when wp is set, wait is asserted high (default). when wp is cleared, wait is asserted low. wait changes state on valid clock edges during active bus cycles (ce# asserted, oe# asserted, rst# deasserted). 10.3.3.1 wait signal function the wait signal indicates data valid when the device is operating in synchronous mode (rcr[15]=0). the wait signal is only ?deasserted? when data is valid on the bus. when the device is operating in synchronous non-array read mode, such as read status, read id, or read query. the wait signal is also ?deasserted? when data is valid on the bus. wait behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. when the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, wait is set to a deasserted state as determined by rcr[10]. see figure 17, ?asynchronous single-word read (adv# latch)? on page 37 , and figure 18, ?asynchronous page-mode read timing? on page 38 . figure 29. example latency count setting using code 3 clk ce# adv# a [max:0] d[15:0] t data code 3 address data 012 34 r103 high-z
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 57 10.3.4 data hold for burst read operations, the data hold (dh) bit determines whether the data output remains valid on dq[15:0] for one or two clock cycles. this period of time is called the ? data cycle ?. when dh is set, output data is held for two clocks (default). when dh is cleared, output data is held for one clock (see figure 30 ). the processor?s data setup time and the flash memory?s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. a method for determining the data hold configuration is shown below: to set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) t data = data set up to clock (defined by cpu) for example, with a clock frequency of 40 mhz, the clock period is 25 ns. assuming t chqv = 20 ns and t data = 4 ns. applying these values to the formula above: 20 ns + 4 ns 25 ns the equation is satisfied and data will be available at every clock period with data hold setting at one clock. if t chqv (ns) + t data (ns) > one clk period (ns), data hold setting of 2 clock periods must be used. table 22. wait functionality table condition wait notes ce# = ?1?, oe# = ?x? or ce# = ?0?, oe# = ?1? high-z 1 ce# =?0?, oe# = ?0? active 1 synchronous array reads active 1 synchronous non-array reads active 1 all asynchronous reads deasserted 1 all writes high-z 1,2 notes: 1. active: wait is asserted until data becomes valid, then deasserts 2. when oe# = v ih during writes, wait = high-z figure 30. data hold timing valid output valid output valid output valid output valid output clk [c] d[15:0] [q] d[15:0] [q] 2 clk data hold 1 clk data hold
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 58 order number: 306666, revision: 005 10.3.5 wait delay the wait delay (wd) bit controls the wait assertion-delay behavior during synchronous burst reads. wait can be asserted either during or one data cycle before valid data is output on dq[15:0]. when wd is set, wait is deasserted one data cycle before valid data (default). when wd is cleared, wait is deasserted during valid data. 10.3.6 burst sequence the burst sequence (bs) bit selects linear-burst sequence (default). only linear-burst sequence is supported. table 23 shows the synchronous burst sequence for all burst lengths, as well as the effect of the burst wrap (bw) setting. 10.3.7 clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for clk. this clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert wait. 10.3.8 burst wrap the burst wrap (bw) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. when performing synchronous burst reads with bw set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. if the burst sequence?s start address is 4-word aligned, then no delay occurs. if the start address is at the end of a 4-word table 23. burst sequence word ordering start addr. (dec) burst wrap (rcr[3]) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5?15-0 1-2-3-4-5-6-7-? 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6?15-0-1 2-3-4-5-6-7-8-? 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7?15-0-1-2 3-4-5-6-7-8-9-? 40 4-5-6-7-0-1-2-3 4-5-6-7-8?15-0-1-2-3 4-5-6-7-8-9-10? 50 5-6-7-0-1-2-3-4 5-6-7-8-9?15-0-1-2-3-4 5-6-7-8-9-10-11? 60 6-7-0-1-2-3-4-5 6-7-8-9-10?15-0-1-2-3-4-5 6-7-8-9-10-11-12-? 70 7-0-1-2-3-4-5-6 7-8-9-10?15-0-1-2-3-4-5-6 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 0 14-15-0-1-2?12-13 14-15-16-17-18-19-20-? 15 0 15-0-1-2-3?13-14 15-16-17-18-19-20-21-? ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5?15-16 1-2-3-4-5-6-7-? 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6?16-17 2-3-4-5-6-7-8-? 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7?17-18 3-4-5-6-7-8-9-? 41 4-5-6-7-8-9-10-11 4-5-6-7-8?18-19 4-5-6-7-8-9-10? 51 5-6-7-8-9-10-11-12 5-6-7-8-9?19-20 5-6-7-8-9-10-11? 61 6-7-8-9-10-11-12-13 6-7-8-9-10?20-21 6-7-8-9-10-11-12-? 71 7-8-9-10-11-12-13-14 7-8-9-10-11?21-22 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 1 14-15-16-17-18?28-29 14-15-16-17-18-19-20-? 15 1 15-16-17-18-19?29-30 15-16-17-18-19-20-21-?
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 59 boundary, the worst case output delay is one clock cycle less than the first access latency count. this delay can take place only once, and doesn?t occur if the burst sequence does not cross a device-row boundary. wait informs the system of this delay when it occurs. 10.3.9 burst length the burst length bit (bl[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 4-word, 8-word, 16-word, and continuous word. continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see table 23, ?burst sequence word ordering? on page 58 ). when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the ?burstable? address space.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 60 order number: 306666, revision: 005 11.0 programming operations the device supports three programming methods: word programming (40h/10h), buffered programming (e8h, d0h), and buffered enhanced factory programming (80h, d0h). see section 9.0, ?device operations? on page 47 for details on the various programming commands issued to the device. the following sections describe device programming in detail. successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be deasserted and the block must be unlocked before attempting to program the block. attempting to program a locked block causes a program error (sr[4] and sr[1] set) and termination of the operation. see section 13.0, ?security modes? on page 68 for details on locking and unlocking blocks. the intel strataflash ? embedded memory (p30) is segmented into multiple 8-mbit programming regions. see section 4.4, ?memory maps? on page 24 for complete addressing. execute in place (xip) applications must partition the memory such that code and data are in separate programming regions. xip is executing code directly from flash memory. each programming region should contain only code or data but not both. the following terms define the difference between code and data. system designs must use these definitions when partitioning their code and data for the p30 device. 11.1 word programming word programming operations are initiated by writing the word program setup command to the device (see section 9.0, ?device operations? on page 47 ). this is followed by a second write to the device with the address and data to be programmed. the device outputs status register data when read. see figure 40, ?word program flowchart? on page 83 . v pp must be above v pplk , and within the specified v ppl min/max values. during programming, the write state machine (wsm) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. programming the flash memory array changes ?ones? to ?zeros?. memory array bits that are zeros can be changed to ones only by erasing the block (see section 12.0, ?erase operations? on page 66 ). the status register can be examined for programming progress and errors by reading at any address. the device remains in the read status register state until another command is written to the device. status register bit sr[7] indicates the programming status while the sequence executes. commands that can be issued to the device during programming are program suspend, read status register, read device identifier, cfi query, and read array (this returns unknown data). when programming has finished, status register bit sr[4] (when set) indicates a programming failure. if sr[3] is set, the wsm could not perform the word programming operation because v pp was outside of its acceptable limits. if sr[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. code: execution code ran out of the flash device on a continuous basis in the system. data: information periodically programmed into the flash device and read back (e.g. execution code shadowed and executed in ram, pictures, log files, etc.).
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 61 before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed. 11.1.1 factory word programming factory word programming is similar to word programming in that it uses the same commands and programming algorithms. however, factory word programming enhances the programming performance with v pp = v pph . this can enable faster programming times during oem manufacturing processes. factory word programming is not intended for extended use. see section 5.2, ?operating conditions? on page 28 for limitations when v pp = v pph . note: when v pp = v ppl , the device draws programming current from the v cc supply. if v pp is driven by a logic signal, v ppl must remain above v ppl min to program the device. when v pp = v pph , the device draws programming current from the v pp supply. figure 31, ?example vpp supply connections? on page 65 shows examples of device power supply configurations. 11.2 buffered programming the device features a 32-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming performance significantly over non-buffered programming. when the buffered programming setup command is issued (see section 9.2, ?device commands? on page 49 ), status register information is updated and reflects the availability of the buffer. sr[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. to retry, issue the buffered programming setup command again, and re-check sr[7]. when sr[7] is set, the buffer is ready for loading. (see figure 42, ?buffer program flowchart? on page 85 ). on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional device addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (a[4:0] = 0x00). crossing a 32-word boundary during programming will double the total programming time. after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if a command other than the buffered programming confirm command is written to the device, a command sequence error occurs and status register bits sr[7,5,4] are set. if an error occurs while writing to the array, the device stops programming, and status register bits sr[7,4] are set, indicating a programming failure. when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming setup command and repeating the buffered program sequence. buffered programming may be performed with v pp = v ppl or v pph (see section 5.2, ?operating conditions? on page 28 for limitations when operating the device with v pp = v pph ).
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 62 order number: 306666, revision: 005 if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command sequence error, and status register bits sr[5,4] are set. if buffered programming is attempted while v pp is below v pplk , status register bits sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 11.3 buffered enhanced factory programming buffered enhanced factory programing (befp) speeds up multi-level cell (mlc) flash programming. the enhanced programming algorithm used in befp eliminates traditional programming elements that drive up overhead in device programmer systems. befp consists of three phases: setup, program/verify, and exit (see figure 43, ?befp flowchart? on page 86 ). it uses a write buffer to spread mlc program performance across 32 data words. verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. host programmer bus cycles fill the device?s write buffer followed by a status check. sr[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. following the buffer-to-flash array programming sequence, the write state machine (wsm) increments internal addressing to automatically select the next 32-word array boundary. this aspect of befp saves host programming equipment the address-bus setup overhead. with adequate continuity testing, programming equipment can rely on the wsm?s internal verification to ensure that the device has programmed properly. this eliminates the external post- program verification and its associated overhead. 11.3.1 befp requirements and considerations befp requirements: ? case temperature: t c = 25 c 5 c ? v cc within specified operating range ? vpp driven to v pph ? target block unlocked before issuing the befp setup and confirm commands ? the first-word address (wa0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired ? wa0 must align with the start of an array buffer boundary 1 befp considerations: ? for optimum performance, cycling must be limited below 100 erase cycles per block 2 ? befp programs one block at a time; all buffer data must fall within a single block 3
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 63 ? befp cannot be suspended ? programming to the flash memory array can occur only when the buffer is full 4 note: 1. word buffer boundaries in the array are determined by a[4:0] (0x00 through 0x1f). the alignment start point is a[4:0] = 0x00. 2. some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. if the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. if the number of words is less than 32, remaining locations must be filled with 0xffff. 11.3.2 befp setup phase after receiving the befp setup and confirm command sequence, status register bit sr[7] (ready) is cleared, indicating that the wsm is busy with befp algorithm startup. a delay before checking sr[7] is required to allow the wsm enough time to perform all of its setups and checks (block-lock status, v pp level, etc.). if an error is detected, sr[4] is set and befp operation terminates. if the block was found to be locked, sr[1] is also set. sr[3] is set if the error occurred due to an incorrect v pp level. note: reading from the device after the befp setup and confirm command sequence outputs status register data. do not issue the read status register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 befp program/verify phase after the befp setup phase has completed, the host programming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr[7] cleared indicates the device is busy and the befp program/verify phase is activated. sr[0] indicates the write buffer is available. two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. for befp, the count value for buffer loading is always the maximum buffer size of 32 words. during the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. programming of the buffer contents to the flash memory array starts as soon as the buffer is full. if the number of words is less than 32, the remaining buffer locations must be filled with 0xffff. caution: the buffer must be completely filled for programming to occur. supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. any data previously loaded into the buffer during the fill cycle is not programmed into the array. the starting address for data entry must be buffer size aligned, if not the befp algorithm will be aborted and the program fails and (sr[4]) flag will be set. data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. the host programming system must poll sr[0] to determine when the buffer program sequence completes. sr[0] cleared indicates that all buffer data has been transferred to the flash array; sr[0] set indicates that the buffer is not available yet for the next fill cycle. the host system may check full
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 64 order number: 306666, revision: 005 status for errors at any time, but it is only necessary on a block basis after befp exit. after the buffer fill cycle, no write cycles should be issued to the device until sr[0] = 0 and the device is ready for the next buffer fill. note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. the host programming system continues the befp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current block?s range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the device enters the befp exit phase. 11.3.4 befp exit phase when sr[7] is set, the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. when exiting the befp algorithm with a block address change, the read mode will not change. after befp exit, any valid command can be issued to the device. 11.4 program suspend issuing the program suspend command while programming suspends the programming operation. this allows data to be accessed from the device other than the one being programmed. the program suspend command can be issued to any device address. a program operation can be suspended to perform reads only. additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see figure 41, ?program suspend/resume flowchart? on page 84 ). when a programming operation is executing, issuing the program suspend command requests the wsm to suspend the programming algorithm at predetermined points. the device continues to output status register data after the program suspend command is issued. programming is suspended when status register bits sr[7,2] are set. suspend latency is specified in section 7.5, ?program and erase characteristics? on page 44 . to read data from the device, the read array command must be issued. read array, read status register, read device identifier, cfi query, and program resume are valid commands during a program suspend. during a program suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at its programming level, and wp# must remain unchanged while in program suspend. if rst# is asserted, the device is reset.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 65 11.5 program resume the resume command instructs the device to continue programming, and automatically clears status register bits sr[7,2]. this command can be written to any address. if error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 41, ?program suspend/resume flowchart? on page 84 ). 11.6 program protection when v pp = v il , absolute hardware write protection is provided for all device blocks. if v pp is at or below v pplk , programming operations halt and sr[3] is set indicating a v pp -level error. block lock registers are not affected by the voltage level on v pp ; they may still be programmed and read, even if v pp is less than v pplk . figure 31. example vpp supply connections ? factory programming with v pp = v pph ? complete write/erase protection when v pp v pplk vcc vpp vcc vpp ? low voltage and factory programming ? low-voltage programming only ? logic control of device protection vcc vpp ? low voltage programming only ? full device protection unavailable vcc vpp 10k v pp v cc v cc prot # v cc v pp =v pph v cc
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 66 order number: 306666, revision: 005 12.0 erase operations flash erasing is performed on a block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 12.1 block erase block erase operations are initiated by writing the block erase setup command to the address of the block to be erased (see section 9.2, ?device commands? on page 49 ). next, the block erase confirm command is written to the address of the block to be erased. if the device is placed in standby (ce# deasserted) during an erase operation, the device completes the erase operation before entering standby.v pp must be above v pplk and the block must be unlocked (see figure 44, ?block erase flowchart? on page 87 ). during a block erase, the write state machine (wsm) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. erasing the flash memory array changes ?zeros? to ?ones?. memory array bits that are ones can be changed to zeros only by programming the block (see section 11.0, ?programming operations? on page 60 ). the status register can be examined for block erase progress and errors by reading any address. the device remains in the read status register state until another command is written. sr[0] indicates whether the addressed block is erasing. status register bit sr[7] is set upon erase completion. status register bit sr[7] indicates block erase status while the sequence executes. when the erase operation has finished, status register bit sr[5] indicates an erase failure if set. sr[3] set would indicate that the wsm could not perform the erase operation because v pp was outside of its acceptable limits. sr[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow once the block erase operation has completed. 12.2 erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any device address. a block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see figure 41, ?program suspend/resume flowchart? on page 84 ). when a block erase operation is executing, issuing the erase suspend command requests the wsm to suspend the erase algorithm at predetermined points. the device continues to output status register data after the erase suspend command is issued. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 7.5, ?program and erase characteristics? on page 44 .
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 67 to read data from the device (other than an erase-suspended block), the read array command must be issued. during erase suspend, a program command can be issued to any block other than the erase-suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read device identifier, cfi query, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock-down are valid commands during erase suspend. during an erase suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at a valid level, and wp# must remain unchanged while in erase suspend. if rst# is asserted, the device is reset. 12.3 erase resume the erase resume command instructs the device to continue erasing, and automatically clears status register bits sr[7,6]. this command can be written to any address. if status register error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 41, ?program suspend/resume flowchart? on page 84 ). 12.4 erase protection when v pp = v il , absolute hardware erase protection is provided for all device blocks. if v pp is below v pplk , erase operations halt and sr[3] is set indicating a v pp -level error.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 68 order number: 306666, revision: 005 13.0 security modes the device features security modes used to protect the information stored in the flash memory array. the following sections describe each security mode in detail. 13.1 block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up in a locked state to protect array data from being altered during power transitions. any block can be locked or unlocked with no latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented using the block lock and block unlock commands. hardware-controlled security can be implemented using the block lock-down command along with asserting wp#. also, v pp data security can be used to inhibit program and erase operations (see section 11.6, ?program protection? on page 65 and section 12.4, ?erase protection? on page 67 ). the p30 device also offers four pre-defined areas in the main array that can be configured as one- time programmable (otp) for the highest level of security. these include the four 32 kb parameter blocks together as one and the three adjacent 128 kb main blocks. this is available for top or bottom parameter devices. 13.1.1 lock block to lock a block, issue the lock block setup command. the next command must be the lock block command issued to the desired block?s address (see section 9.2, ?device commands? on page 49 and figure 46, ?block lock operations flowchart? on page 89 ). if the set read configuration register command is issued after the block lock setup command, the device configures the rcr instead. block lock and unlock operations are not affected by the voltage level on v pp . the block lock bits may be modified and/or read even if v pp is at or below v pplk . 13.1.2 unlock block the unlock block command is used to unlock blocks (see section 9.2, ?device commands? on page 49 ). unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the device is reset or powered down. if a block is in a lock-down state, wp# must be deasserted before it can be unlocked (see figure 32, ?block locking state diagram? on page 69 ). 13.1.3 lock-down block a locked or unlocked block can be locked-down by writing the lock-down block command sequence (see section 9.2, ?device commands? on page 49 ). blocks in a lock-down state cannot be programmed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can only be unlocked by issuing the unlock block command with wp# deasserted. to return an unlocked block to locked-
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 69 down state, a lock-down command must be issued prior to changing wp# to v il . locked-down blocks revert to the locked state upon reset or power up the device (see figure 32, ?block locking state diagram? on page 69 ). 13.1.4 block lock status the read device identifier command is used to determine a block?s lock status (see section 14.2, ?read device identifier? on page 74 ). data bits dq[1:0] display the addressed block?s lock status; dq0 is the addressed block?s lock bit, while dq1 is the addressed block?s lock-down bit. 13.1.5 block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr[7] and sr[6] are set, indicating the device is suspended and ready to accept another command. next, write the desired lock command sequence to a block, which changes the lock state of that block. after completing block lock or unlock operations, resume the erase operation using the erase resume command. note: a lock block setup command followed by any command other than lock block, unlock block, or lock-down block produces a command sequence error and set status register bits sr[4] and sr[5]. if a command sequence error occurs during an erase suspend, sr[4] and sr[5] remains set, even after the erase operation is resumed. unless the status register is cleared using the clear figure 32. block locking state diagram [x00] [x01] p ower-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, dq1, dq0]. x = don?t care. 2. dq1 indicates block lock-down status. dq1 = ?0?, lock-down has not been issued to this block. dq1 = ?1?, lock-down has been issued to this block. 3. dq0 indicates block lock status. dq0 = ?0?, block is unlocked. dq0 = ?1?, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 70 order number: 306666, revision: 005 status register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is resumed. block lock operations cannot occur during a program suspend. see appendix a, ?write state machine? on page 76 , which shows valid commands during an erase suspend. 13.2 selectable one-time programmable blocks any of four pre-defined areas from the main array (the four 32 kb parameter blocks together as one and three adjacent 128 kb main blocks) can be configured as one-time programmable (otp) so further program and erase operations are not allowed. this option is available for top or bottom parameter devices. please see your local intel representative for details about the selectable otp implementation. table 24. selectable otp block mapping density top parameter configuration bottom parameter configuration 256-mbit blocks 258:255 (parameters) blocks 3:0 (parameters) block 254 (main) block 4 (main) block 253 (main) block 5 (main) block 252 (main) block 6 (main) 128-mbit blocks 130:127 (parameters) blocks 3:0 (parameters) block 126 (main) block 4 (main) block 125 (main) block 5 (main) block 124 (main) block 6 (main) 64-mbit blocks 66:63 (parameters) blocks 3:0 (parameters) block 62 (main) block 4 (main) block 61 (main) block 5 (main) block 60 (main) block 6 (main) note: the 512-mbit devices will have multiple selectable otp areas depending on the number of 256-mbit dies in the stack and the placement of the parameter blocks.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 71 13.3 protection registers the device contains 17 protection registers (prs) that can be used to implement system security measures and/or device identification. each protection register can be individually locked. the first 128-bit protection register is comprised of two 64-bit (8-word) segments. the lower 64- bit segment is pre-programmed at the intel factory with a unique 64-bit number. the other 64-bit segment, as well as the other sixteen 128-bit protection registers, are blank. users can program these registers as needed. when programmed, users can then lock the protection register(s) to prevent additional bit programming (see figure 33, ?protection register map? on page 71 ). the user-programmable protection registers contain one-time programmable (otp) bits; when programmed, register bits cannot be erased. each protection register can be accessed multiple times to program individual bits, as long as the register remains unlocked. each protection register has an associated lock register bit. when a lock register bit is programmed, the associated protection register can only be read; it can no longer be programmed. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when a protection register is locked, it cannot be unlocked. . figure 33. protection register map 0x89 lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 128-bit protection register 16 (user-programmable) 128-bit protection register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 72 order number: 306666, revision: 005 13.3.1 reading the protection registers the protection registers can be read from any address. to read the protection register, first issue the read device identifier command at any address to place the device in the read device identifier state (see section 9.2, ?device commands? on page 49 ). next, perform a read operation using the address offset corresponding to the register to be read. table 26, ?device identifier information? on page 75 shows the address offsets of the protection registers and lock registers. register data is read 16 bits at a time. 13.3.2 programming the protection registers to program any of the protection registers, first issue the program protection register command at the parameter?s base address plus the offset to the desired protection register (see section 9.2, ?device commands? on page 49 ). next, write the desired protection register data to the same protection register address (see figure 33, ?protection register map? on page 71 ). the device programs the 64-bit and 128-bit user-programmable protection register data 16 bits at a time (see figure 47, ?protection register programming flowchart? on page 90 ). issuing the program protection register command outside of the protection register?s address space causes a program error (sr[4] set). attempting to program a locked protection register causes a program error (sr[4] set) and a lock error (sr[1] set). 13.3.3 locking the protection registers each protection register can be locked by programming its respective lock bit in the lock register. to lock a protection register, program the corresponding bit in the lock register by issuing the program lock register command, followed by the desired lock register data (see section 9.2, ?device commands? on page 49 ). the physical addresses of the lock registers are 0x80 for register 0 and 0x89 for register 1. these addresses are used when programming the lock registers (see table 26, ?device identifier information? on page 75 ). bit 0 of lock register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit protection register containing the unique identification number of the device. bit 1 of lock register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit protection register. when programming bit 1 of lock register 0, all other bits need to be left as ?1? such that the data programmed is 0xfffd. lock register 1 controls the locking of the upper sixteen 128-bit protection registers. each of the 16 bits of lock register 1 correspond to each of the upper sixteen 128-bit protection registers. programming a bit in lock register 1 locks the corresponding 128-bit protection register. caution: after being locked, the protection registers cannot be unlocked.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 73 14.0 special read states the following sections describe non-array read states. non-array reads can be performed in asynchronous read or synchronous burst mode. a non-array read operation occurs as asynchronous single-word mode. when non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. when a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. refer to the following waveforms for more detailed information: ? figure 16, ?asynchronous single-word read (adv# low)? on page 37 ? figure 17, ?asynchronous single-word read (adv# latch)? on page 37 ? figure 19, ?synchronous single-word array or non-array read timing? on page 38 14.1 read status register to read the status register, issue the read status register command at any address. status register information is available to which the read status register, word program, or block erase command was issued. status register data is automatically made available following a word program, block erase, or block lock command sequence. reads from the device after any of these command sequences outputs the device?s status until another valid command is written (e.g. read array command). the status register is read using single asynchronous-mode or synchronous burst mode reads. status register data is output on dq[7:0], while 0x00 is output on dq[15:8]. in asynchronous mode the falling edge of oe#, or ce# (whichever occurs first) updates and latches the status register contents. however, reading the status register in synchronous burst mode, ce# or adv# must be toggled to update status data. the device write status bit (sr[7]) provides overall status of the device. status register bits sr[6:1] present status and error information about the program, erase, suspend, v pp , and block- locked operations. table 25. status register description (sheet 1 of 2) status register (sr) default value = 0x80 device write status erase suspend status erase status program status v pp status program suspend status block- locked status befp status dws ess es ps vpps pss bls bws 76543210 bit name description 7 device write status (dws) 0 = device is busy; program or erase cycle in progress; sr[0] valid. 1 = device is ready; sr[6:1] are valid. 6 erase suspend status (ess) 0 = erase suspend not in effect. 1 = erase suspend in effect.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 74 order number: 306666, revision: 005 note: always clear the status register prior to resuming erase operations. it avoids status register ambiguity when issuing commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register contains the command sequence error status (sr[7,5,4] set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the status register because it contains the previous error status. 14.1.1 clear status register the clear status register command clears the status register. it functions independent of v pp . the write state machine (wsm) sets and clears sr[7,6,2], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. 14.2 read device identifier the read device identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data (see section 9.2, ?device commands? on page 49 for details on issuing the read device identifier command). table 26, ?device identifier information? on page 75 and table 27, ?device id codes? on page 75 show the address offsets and data values for this device. 5 erase status (es) 0 = erase successful. 1 = erase fail or program sequence error when set with sr[4,7]. 4 program status (ps) 0 = program successful. 1 = program fail or program sequence error when set with sr[5,7] 3v pp status (vpps) 0 = vpp within acceptable limits during program or erase operation. 1 = vpp < vpplk during program or erase operation. 2 program suspend status (pss) 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked status (bls) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 befp status (bws) after buffered enhanced factory programming (befp) data is loaded into the buffer: 0 = befp complete. 1 = befp in-progress. table 25. status register description (sheet 2 of 2) status register (sr) default value = 0x80
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 75 14.3 cfi query the cfi query command instructs the device to output common flash interface (cfi) data when read. see section 9.2, ?device commands? on page 49 for details on issuing the cfi query command. appendix c, ?common flash interface? on page 91 shows cfi information and address offsets within the cfi database. table 26. device identifier information item address (1) data manufacturer code 0x00 0089h device id code 0x01 id (see table 27 ) block lock configuration: bba + 0x02 lock bit: ? block is unlocked dq 0 = 0b0 ? block is locked dq 0 = 0b1 ? block is not locked-down dq 1 = 0b0 ? block is locked-down dq 1 = 0b1 read configuration register 0x05 rcr contents lock register 0 0x80 pr-lk0 64-bit factory-programmed protection register 0x81?0x84 factory protection register data 64-bit user-programmable protection register 0x85?0x88 user protection register data lock register 1 0x89 protection register data 128-bit user-programmable protection registers 0x8a?0x109 pr-lk1 notes: 1. bba = block base address. table 27. device id codes id code type device density device identifier codes ?t (top parameter) ?b (bottom parameter) device code 64-mbit 8817 881a 128-mbit 8818 881b 256-mbit 8919 891c note: the 512-mbit devices do not have a device id associated with them. each die within the stack can be identified by either of the 256-mbit device id codes depending on its parameter option.
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 76 order number: 306666, revision: 005 appendix a write state machine figure 34 through figure 39 show the command state transitions (next state table) based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last read state (read array, read device id, cfi query or read status register) until a new command changes it. the next wsm state does not depend on the partition?s output state. figure 34. write state machine?next state table (sheet 1 of 6) read array (2) word program (3,4) buffered program (bp) erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb, confirm (8) bp / prg / erase suspend read status clear status register (5) read id/query lock, unlock, lock-down , cr setup (4) (ffh) (10h/40h) (e8h) (20h) (80h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) ready program setup bp setup erase setup befp setup lock/cr setup ready (unlock block) setup busy setup busy word program suspend suspend word program busy setup bp load 1 bp load 2 bp confirm bp busy bp busy bp suspend bp suspend bp busy setup erase busy busy erase suspend suspend erase suspend word program setup in erase suspend bp setup in erase suspend erase busy lock/cr setup in erase suspend bp suspend erase bp busy erase busy erase suspend erase suspend ready (error) erase busy bp suspend ready (error) word program program busy word program suspend word program busy otp ready (lock error) ready ready ready (lock error) otp busy current chip state (7) command input to chip and resulting chip next state bp bp busy lock/cr setup bp load 2 ready (error) ready (error) word program busy bp confirm if data load into program buffer is complete; else bp load 2 word program suspend bp load 1
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 77 figure 35. write state machine?next state table (sheet 2 of 6) setup busy word program suspend in erase suspend suspend word program busy in erase suspend setup bp load 1 bp load 2 bp confirm bp busy in erase suspend bp busy bp suspend in erase suspend bp suspend bp busy in erase suspend erase suspend (unlock block) setup befp loading data (x=32) erase suspend (error) erase suspend (lock error [botch]) ready (error) ready (error) bp suspend in erase suspend ready (error in erase suspend) bp busy in erase suspend bp suspend in erase suspend bp busy in erase suspend word program busy in erase suspend word program in erase suspend word program busy in erase suspend word program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) bp confirm if data load into program buffer is complete; else bp load 2 bp in erase suspend bp load 2 word program busy in erase suspend busy word program suspend in erase suspend befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. ( 7) befp busy buffered enhanced factory program mode bp load 1 read array (2) word program (3,4) buffered program (bp) erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb, confirm (8) bp / prg / erase suspend read status clear status register (5) read id/query lock, unlock, lock-down , cr setup (4) (ffh) (10h/40h) (e8h) (20h) (80h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) current chip state (7) command input to chip and resulting chip next state
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 78 order number: 306666, revision: 005 figure 36. write state machine?next state table (sheet 3 of 6) setup busy setup busy suspend setup bp load 1 bp load 2 bp confirm bp busy bp suspend setup busy suspend erase word program otp ready current chip state (7) bp lock/cr setup otp setup (4) lock block confirm (8) lock-down block confirm (8) write rcr confirm (8) block address (?wa0) 9 illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (xxxxh) (all other c odes) otp setup ready (lock error) r eady (lock block) r eady (lock down blk) r eady (set cr) ready n/a ready ready (bp load 2 bp load 2 ready bp confirm if data load into program buffer is complete; else bp load 2 ready (error) (proceed if unlocked or lock error) ready (error) ready ready n/a bp confirm if data load into program buffer is complete; else bp load 2 ready (error) bp busy erase busy word program suspend bp load 1 bp load 2 otp busy word program busy word program busy wsm operation completes command input to chip and resulting chip next state n/a ready (lock error) ready bp suspend ready (error) erase suspend n/a n/a
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 79 figure 37. write state machine?next state table (sheet 4 of 6) otp setup (4) lock block confirm (8) lock-down block confirm (8) write rcr confirm (8) block address (?wa0) 9 illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (xxxxh) (all other codes) wsm operation completes command input to chip and resulting chip next state current chip state (7) na erase suspen d n/a ready (bp load 2 bp load 2 ready bp confirm if data load into program buffer is complete; else bp load 2 ready (error) (proceed if unlocked or lock error) ready (error) erase suspen d erase suspend (lock error) erase suspend (lock block) erase suspend (lock down block) erase suspend (set cr) ready (befp loading data) ready (error) befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. (7) bp load 1 ready (error) bp confirm if data load into program buffer is complete; else bp load 2 ready (error in erase suspend) word program suspend in erase suspend bp load 2 ready word program busy in erase suspend busy word program busy in erase suspend befp busy ready erase suspend (lock error) n/a bp busy in erase suspend bp suspend in erase suspend n/a setup busy suspend setup bp load 1 bp load 2 bp confirm bp busy bp suspend setup befp busy buffered enhanced factory program mode lock/cr setup in erase suspend bp in erase suspend word program in erase suspend
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 80 order number: 306666, revision: 005 figure 38. write state machine?next state table (sheet 5 of 6) read array (2) word program setup (3,4) bp setup erase setup (3,4) buffered enhanced factory pgm setup (3, 4) be confirm, p/e resume, ulb confirm (8) program/ erase suspend read status clear status register (5) read id/query lock, unlock, lock-down , cr setup (4) (ffh) (10h/40h) (e8h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) status read command input to chip and resulting output mux next state output next state table status read output mux does not change. status read id read status read ready, erase suspend, bp suspend status read lock/cr setup, lock/cr setup in erase susp output does not change. status read befp setup, befp pgm & verify busy, erase setup, otp setup, bp: setup , load 1, load 2, confirm, word pgm setup, word pgm setup in erase susp, bp setup, load1, load 2, confirm in erase suspend current chip state otp busy bp busy, word program busy, erase busy, bp busy bp busy in erase suspend word pgm suspend, word pgm busy in erase suspend, pgm suspend in erase suspend read array
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 81 notes: 1. "illegal commands" include commands outside of the allowed command set (allowed commands: 40h [pgm], 20h [erase], etc.) 2. if a "read array" is attempted from a busy partition, the result will be invalid data. the id and query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. to protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. for example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xd0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. figure 39. write state machine?next state table (sheet 6 of 6) otp busy bp busy, word program busy, erase busy, bp busy bp busy in erase suspend word pgm suspend, word pgm busy in erase suspend, pgm suspend in erase suspend befp setup, befp pgm & verify busy, erase setup, otp setup, bp: setup , load 1, load 2, confirm, word pgm setup, word pgm setup in erase susp, bp setup, load1, load 2, confirm in erase suspend current chip state ready, erase suspend, bp suspend lock/cr setup, lock/cr setup in erase susp otp setup (4) lock block confirm (8) lock-down block confirm (8) write cr confirm (8) block address (?wa0) illegal cmds or befp data (1) (c0h) (01h) (2fh) (03h) (ffffh) (all other codes) wsm operation completes output does not change. a rray read s tatus read array read output does not change. output does not change. status read status read status read command input to chip and resulting output mux next state output next state table
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 82 order number: 306666, revision: 005 5. the clear status command only clears the error bits in the status register if the device is not in the following modes: wsm running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, befp modes). 6. befp writes are only allowed when the status register bit #0 = 0, or else the data is ignored. 7. the "current state" is that of the "chip" and not of the "partition"; each partition "remembers" which output (array, id/cfi or status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 8. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. 9. wa0 refers to the block address latched during the first write cycle of the current operation.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 83 appendix b flowcharts figure 40. word program flowchart program suspend loop start write 0x40, word address write data, word address read status register sr[7] = full status check (if desired) program complete suspend? 1 0 no yes word program procedure repeat for subsequent word program operations. full status register check can be done after each program, o r after a sequence of program operations. write 0xff after the last operation to set to the read array state. comments bus operation command data = 0x40 addr = location to program write program setup data = data to program addr = location to program write data status register data read none check sr[7] 1 = wsm ready 0 = wsm busy idle none (setup) (confirm) full status check procedure read status register program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device protect error program error if an error is detected, clear the status register before continuing operations - only the clear staus register command clears the status register error bits. idle idle bus operation none none command check sr[3]: 1 = v pp error check sr[4]: 1 = data program error comments idle none check sr[1]: 1 = block locked; operation aborted
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 84 order number: 306666, revision: 005 figure 41. program suspend/resume flowchart r ead status register sr.7 = sr.2 = wr i te ffh susp parti tion read array data program completed done reading wr ite ffh pgm'd partition wr i te d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure wr ite program resume data = d0h addr = suspended block (ba) bus operation command comments wr ite program suspend data = b0h addr = block to suspend (ba) standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed wr ite read array data = ffh addr = any address within the suspended partition read read array data from block other than the one being programmed read status register data addr = suspended block (ba) pgm_sus.wm f start wr i te b0h any address program suspend read status program resume read array read array write 70h same partition wr ite read status data = 70h addr = same partition if the suspended partition was placed in read a rray mode: wr ite read status return partition to status mode: data = 70h addr = same partition write 70h same partition read status
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 85 figure 42. buffer program flowchart buffer programming procedure start get next target address issue buffer prog. cmd. 0xe8, word address read status register at word address write buffer available? sr[7] = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired? write confirm 0xd0 and word address (note 5) yes no buffer program data, start word address x = 0 0 = no yes use single word programming abort buffer program? no x = n? write buffer data, word address x = x + 1 write to another block address buffer program aborted no yes yes write word count, word address suspend program loop read status register (note 7) is bp finished? sr[7] = full status check if desired program complete suspend program? 1=yes 0=no yes no issue read status register command no 1. word count value on d[7:0] is loaded into the word count register. count ranges for this device are n = 0x00 to 0x1f. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the issued word address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a[4:0] of the start word address = 0x00). 5. the buffered programming confirm command must be issued to an address in the same block, for example, the original start word address, or the last address used during the loop that loaded the buffer data. 6. the status register indicates an improper command sequence if the buffer program command is aborted; use the clear status register command to clear error bits. 7. the status register can be read from any address within the programming partition. full status check can be done after all erase and write sequences complete. write 0xff after the last operation to place the partition in the read array state. bus operation idle read command none none wri t e buffer prog. setup read none idle none comments check sr[7]: 1 = wsm ready 0 = wsm busy status register data addr = note 7 data = 0xe8 addr = word address sr[7] = valid addr = word address check sr[7]: 1 = write buffer available 0 = no write buffer available wri t e (notes 5, 6) buffer prog. conf. data = 0xd0 addr = original word address wri t e (notes 1, 2) none data = n-1 = word count n = 0 corresponds to count = 1 addr = word address wri t e (notes 3, 4) none data = write buffer data addr = start word address wri t e (note 3) none data = write buffer data addr = word address other partitions of the device can be read by addressing those partitions and driving oe# low. (any write commands are not allowed during this period.) 0xff commands can be issued to read from any blocks in other partitions
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 86 order number: 306666, revision: 005 figure 43. befp flowchart notes: 1. first-word address to be programmed within the target block must be aligned on a write -buffer boundary. 2. write-buffer contents are programmed sequentially to the flash array starting at the first word address (wsm internally incr ements addressing). befp exit repeat for subsequent blocks ; after befp exit, a full status register check can determine if any program error occurred; see full status register check procedure in the word program flowchart. write 0xff to enter read array state. standby read bus state operation status register check exit status comments data = status register data address = 1 st word addr. check sr [7]: 0 = exit not completed 1 = exit completed befp setup comments bus state operation write (note 1) befp setup write befp confirm read status register standby befp setup done? write unlock block data = 0x80 @ 1 st word address data = 0x80 @ 1 st word address 1 data = status register data address = 1 st word addr. check sr[7]: 0 = befp ready 1 = befp not ready v pph applied to vpp standby error condition check if sr[7] is set, check: sr[3] set = v pp error sr[1] set = locked block no (sr[0]=1) write data @ 1 st word address last data? write 0xffff, address not within current block program done? read status reg. yes (sr[0]=0) y no (sr[7]=0) full status check procedure program complete read status reg. befp exited? yes (sr[7]=1) start write 80h @ 1 st word address v pp applied block unlocked write d0h @ 1 st word address befp setup done? read status reg. no (sr[7]=1) exit n program & verify phase exit phase setup phase buffered enhanced factory programming (befp) procedure check x = 32? initialize count: x = 0 increment count: x = x+1 y n check v pp , lock errors (sr[3,1]) yes (sr[7]=0) befp setup delay data stream ready? read status reg. yes (sr[0]=0) no (sr[0]=1) befp program & verify comments bus state write (note 2) load buffer standby increment count standby initialize count data = data to program address = 1 st word addr. x = x+1 x = 0 read status register standby program done? data = status reg. data address = 1 st word addr. check sr[0]: 0 = program done 1 = program in progress write exit prog & verify phase data = 0xffff @ address not in current block standby last data? no = fill buffer again yes = exit standby buffer full? x = 32? yes = read sr[0] no = load next data word read standby status register data stream ready? data = status register data address = 1 st word addr. check sr[0]: 0 = ready for data 1 = not ready for data operation
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 87 figure 44. block erase flowchart start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. write 0xff after the last operation to enter read array mode. only the clear status register command clears sr[1, 3, 4, 5 ]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 write 0x20, block address write 0xd0, block address read status register sr[7] = full erase status check (if desired) block erase complete read status register block erase successful sr[1] = block locked error block erase procedure bus operation command comments write block erase setup data = 0x20 addr = block to be erased (ba) write erase confirm data = 0xd0 addr = block to be erased (ba) read none status register data. idle none check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = command sequence error sr[5] = block erase error idle none check sr[3]: 1 = v pp range error idle none check sr[4,5]: both 1 = command sequence error idle none check sr[5]: 1 = block erase error idle none check sr[1]: 1 = attempted erase of locked block; erase aborted. (block erase) (erase confirm)
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 88 order number: 306666, revision: 005 figure 45. erase suspend/resume flowchart erase completed read array data 0 0 no read 1 program program loop read array data 1 start r ead status register sr[7] = sr[6] = erase resumed read or program? done wr i te wr i te idle idle wr i te erase suspend read array or program none none program resume data = 0xb0 addr = same partition address as above data = 0xff or 0x40 addr = any address within the suspended partition check sr[7]: 1 = wsm r eady 0 = wsm busy check sr[6]: 1 = erase suspended 0 = erase completed data = 0xd0 addr = any address bus operation command comments read none status register data. addr = same partition read or wr i te none r ead ar r ay or pr ogr am data fr om /to bl ock other than the one being er ased erase suspend / resume procedure if t he su sp end ed part it ion was p laced in read array mode or a program loop: wr i te 0x b0, any address (e ra se s u spe nd ) write 0x70, same parti tion (read status) wr i te 0x d 0, any address ( erase resume) write 0x70, same parti tion (read status) wr ite 0xff, erased partition (read array) wr i te read status data = 0x70 addr = any par ti tion addr ess wr i te read status register return partition to status mode: data = 0x70 addr = same partition
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 89 figure 46. block lock operations flowchart no start write 0x60, block address write 0x90 read block lock status locking change? lock change complete write either 0x01/0xd0/0x2f, block address write 0xff partition address yes write write write (optional) read (optional) idle write lock setup lock, unlock, or lock-down confirm read device id block lock status none read array data = 0x60 addr = block to lock/unlock/lock-down data = 0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr = block to lock/unlock/lock-down data = 0x90 addr = block address + offset 2 block lock status data addr = block address + offset 2 confirm locking change on d[1,0]. data = 0xff addr = block address bus operation command comments locking operations procedure (lock confirm) (read device id) (read array) optional (lock setup)
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 90 order number: 306666, revision: 005 figure 47. protection register programming flowchart full status check procedure program protection register operation addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program, o r after a sequence of program operations. write 0xff after the last operation to set read array state. only the clear staus register command clears sr[1, 3, 4]. if an error is detected, clear the status register before attempting a program retry or other error recovery. 1 0 1 1 1 protection register programming procedure start write 0xc0, pr address write pr address & data read status register sr[7] = full status check (if desired) program complete read status register data program successful sr[3] = sr[4] = sr[1] = v pp range error program error register locked; program aborted idle idle bus operation none none command check sr[3]: 1 =v pp range error check sr[4]: 1 =programming error comments write write idle program pr setup protection program none data = 0xc0 addr = first location to program data = data to program addr = location to program check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments read none status register data. idle none check sr[1]: 1 =block locked; operation aborted (program setup) (confirm data) 0 0 0
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 91 appendix c common flash interface the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the cfi query command (see section 9.2, ?device commands? on page 49 ). system software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq 7-0 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ?q? in the low byte (dq 7-0 ) and 00h in the high byte (dq 15-8 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 28. summary of query structure output as a function of device and mode device hex offset hex code ascii value 00010: 51 "q" device addresses 00011: 52 "r" 00012: 59 "y"
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 92 order number: 306666, revision: 005 table 29. example of query structure output of x16- devices c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized below. table 30. query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 32-kword). 3. offset 15 defines ?p? which points to the primary intel-specific extended query table. word addressing: byte addressing: offset hex code value offset hex code value a x ?a 0 d 15 ?d 0 a x ?a 0 d 7 ?d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id lo prvendor 00013h p_id lo prvendor 00014h p_id hi id # 00014h p_id lo id # 00015h p lo prvendor 00015h p_id hi id # 00016h p hi tbladr 00016h ... ... 00017h a_id lo altvendor 00017h 00018h a_id hi id # 00018h ... ... ... ... offset sub-section name description (1) 00001-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 93 c.3 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 31. cfi identification table 32. system interface information offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --20 2.0v 1dh 1 1d: --85 8.5v 1eh 1 1e: --95 9.5v 1fh 1 ?n? such that typical single word program time-out = 2 n -sec 1f: --08 256s 20h 1 ?n? such that typical max. buffer write time-out = 2 n -sec 20: --09 512s 21h 1 ?n? such that typical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ?n? such that typical full chip erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --01 512s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --01 1024 s 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --02 4s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 94 order number: 306666, revision: 005 c.4 device geometry definition table 33. device geometry definition offset length description code 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 ? ? ? ? x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ????????29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --06 64 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0?15 = y, y+1 = number of identical-size erase blocks 32: bits 16?31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region address 64-mbit ?b ?t ?b ?t ?b ?t 27: --17 --17 --18 --18 --19 --19 28: --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 2a: --06 --06 --06 --06 --06 --06 2b: --00 --00 --00 --00 --00 --00 2c: --02 --02 --02 --02 --02 --02 2d: --03 --3e --03 --7e --03 --fe 2e: --00 --00 --00 --00 --00 --00 2f: --80 --00 --80 --00 --80 --00 30: --00 --02 --00 --02 --00 --02 31: --3e --03 --7e --03 --fe --03 32: --00 --00 --00 --00 --00 --00 33: --00 --80 --00 --80 --00 --80 34: --02 --00 --02 --00 --02 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 128-mbit 256-mbit
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 95 c.5 intel-specific extended query table table 34. primary vendor-specific extended query discrete ?b ?t ?- ?- die 1 (b) die 2 (t) die 1 (t) die 2 (b) 112: --00 --00 --40 --00 --40 --00 512-mbit address ?b ?t die 1 (b) die 2 (t) die 3 (b) die 4 (t) die 1 (t) die 2 (b) die 3 (t) die 4 (b) 112: --40 --00 --40 --00 --40 --00 --40 --00 1-gbit ?t address ?b offset (1) length description hex p = 10ah (optional flash features and commands) add. code value (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string ?pri? 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --34 "4" (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --e6 (p+6)h bits 11?29 are reserved; undefined bits are ?0.? if bit 31 is 110: --01 (p+7)h ?1? then another 31 bit field of optional features follows at 111: --00 (p+8)h the end of the bit?30 field. 112: bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 0 no bit 10 extended flash array blocks supported bit 10 = 0 no bit 30 cfi link(s) to follow bit 30 bit 31 another "optional features" field to follow bit 31 (p+9)h 1 113: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 114: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 115: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes bit 4 efa block lock-bit status register active bit 4 = 0 no bit 5 efa block lock-down bit status active bit 5 = 0 no (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v see table below see table below v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 96 order number: 306666, revision: 005 table 35. protection register information table 36. burst read information offset (1) length description hex p = 10ah (optional flash features and commands) add. code value (p+e)h 1 118: --02 2 (p+f)h 4 protection field 1: protection description 119: --80 80h (p+10)h this field describes user-available one time programmable 11a: --00 00h (p+11)h (otp) protection register bytes. some are pre-programmed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 protection field 2: protection description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40?47 = ?n? n = factory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 48?55 = ?n? \ 2n = factory programmable bytes/group bits 56?63 = ?n? n = user pgm'd groups (low byte) bits 64?71 = ?n? n = user pgm'd groups (high byte) bits 72?79 = ?n? 2 n = user programmable bytes/group with device-unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec-plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes bits 0?31 point to the protection register physical lock-word address in the jedec-plane. following bytes are factory or user-programmable. bits 32?39 = ?n? n = factory pgm'd groups (low byte) number of protection register fields in jedec id space. ?00h,? indicates that 256 protection fields are available offset (1) length description hex p = 10ah (optional flash features and commands) add. code value (p+1d)h 1 127: --03 8 byte (p+1e)h 1 128: --04 4 (p+1f)h 1 129: --01 4 (p+20)h 1 synchronous mode read capability configuration 2 12a: --02 8 (p+21)h 1 synchronous mode read capability configuration 3 12b: --03 16 (p+22)h 1 synchronous mode read capability configuration 4 12c: --07 cont page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3?7 = reserved bits 0?2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0?2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width.
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 97 table 37. partition and erase block region information table 38. partition region 1 information offset (1) see table below p = 10ah description address bottom top (optional flash features and commands) len bot top (p+23)h (p+23)h 112d:12d: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. offset (1) see table below p = 10ah description address bottom top (optional flash features and commands) len bot top (p+24)h (p+24)h data size of this parition region information field 2 12e: 12e (p+25)h (p+25)h (# addressable locations, including this field) 12f 12f (p+26)h (p+26)h number of identical partitions within the partition region 2 130: 130: (p+27)h (p+27)h 131: 131: (p+28)h (p+28)h 1 132: 132: (p+29)h (p+29)h 1 133: 133: (p+2a)h (p+2a)h 1 134: 134: (p+2b)h (p+2b)h 1 135: 135: types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes) number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 98 order number: 306666, revision: 005 table 39. partition region 1 information (continued) offset (1) see table below p = 10ah description address bottom top (optional flash features and commands) len bot top (p+2c)h (p+2c)h partition region 1 erase block type 1 information 4 136: 136: (p+2d)h (p+2d)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 137: 137: (p+2e)h (p+2e)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 138: 138: (p+2f)h (p+2f)h 139: 139: (p+30)h (p+30)h partition 1 (erase block type 1) 2 13a: 13a: (p+31)h (p+31)h block erase cycles x 1000 13b: 13b: (p+32)h (p+32)h 1 13c: 13c: (p+33)h (p+33)h 1 13d: 13d: partition region 1 (erase block type 1) programming region information 6 (p+34)h (p+34)h bits 0?7 = x, 2^x = programming region aligned size ( bytes ) 13e: 13e: (p+35)h (p+35)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 13f: 13f: (p+36)h (p+36)h bits 16?23 = y = control mode valid size in bytes 140: 140: (p+37)h (p+37)h bits 24-31 = reserved 141: 141: (p+38)h (p+38)h bits 32-39 = z = control mode invalid size in bytes 142: 142: (p+39)h (p+39)h bits 40-46 = reserved; bit 47 = legacy flash operation (ignore 23:16 & 39:32) 143: 143: (p+3a)h (p+3a)h partition region 1 erase block type 2 information 4 144: 144: (p+3b)h (p+3b)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 145: 145: (p+3c)h (p+3c)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 146: 146: (p+3d)h (p+3d)h 147: 147: (p+3e)h (p+3e)h partition 1 (erase block type 2) 2 148: 148: (p+3f)h (p+3f)h block erase cycles x 1000 149: 149: (p+40)h (p+40)h 1 14a: 14a: (p+41)h (p+41)h 1 14b: 14b: partition region 1 (erase block type 2) programming region information 6 (p+42)h (p+42)h bits 0?7 = x, 2^x = programming region aligned size ( bytes ) 14c: 14c: (p+43)h (p+43)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 14d: 14d: (p+44)h (p+44)h bits 16?23 = y = control mode valid size in bytes 14e: 14e: (p+45)h (p+45)h bits 24-31 = reserved 14f: 14f: (p+46)h (p+46)h bits 32-39 = z = control mode invalid size in bytes 150: 150: (p+47)h (p+47)h bits 40-46 = reserved; bit 47 = legacy flash operation (ignore 23:16 & 39:32) 151: 151: partition 1 (erase block type 1) page mode and synchronous mode capab ilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 1 (erase block type 1) bits per cell; internal edac bits 0?3 = bits per cell in erase region bit 4 = internal edac used (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 2) bits per cell; internal edac bits 0?3 = bits per cell in erase region bit 4 = internal edac used (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 2) page mode and synchronous mode capab ilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 99 table 40. partition and erase block region information address 64-mbit ?b ?t ?b ?t ?b ?t 12d: --01 --01 --01 --01 --01 --01 12e: --24 --24 --24 --24 --24 --24 12f: --00 --00 --00 --00 --00 --00 130: --01 --01 --01 --01 --01 --01 131: --00 --00 --00 --00 --00 --00 132: --11 --11 --11 --11 --11 --11 133: --00 --00 --00 --00 --00 --00 134: --00 --00 --00 --00 --00 --00 135: --02 --02 --02 --02 --02 --02 136: --03 --3e --03 --7e --03 --fe 137: --00 --00 --00 --00 --00 --00 138: --80 --00 --80 --00 --80 --00 139: --00 --02 --00 --02 --00 --02 13a: --64 --64 --64 --64 --64 --64 13b: --00 --00 --00 --00 --00 --00 13c: --02 --02 --02 --02 --02 --02 13d: --03 --03 --03 --03 --03 --03 13e: --00 --00 --00 --00 --00 --00 13f: --80 --80 --80 --80 --80 --80 140: --00 --00 --00 --00 --00 --00 141: --00 --00 --00 --00 --00 --00 142: --00 --00 --00 --00 --00 --00 143: --80 --80 --80 --80 --80 --80 144: --3e --03 --7e --03 --fe --03 145: --00 --00 --00 --00 --00 --00 146: --00 --80 --00 --80 --00 --80 147: --02 --00 --02 --00 --02 --00 148: --64 --64 --64 --64 --64 --64 149: --00 --00 --00 --00 --00 --00 14a: --02 --02 --02 --02 --02 --02 14b: --03 --03 --03 --03 --03 --03 14c: --00 --00 --00 --00 --00 --00 14d: --80 --80 --80 --80 --80 --80 14e: --00 --00 --00 --00 --00 --00 14f: --00 --00 --00 --00 --00 --00 150: --00 --00 --00 --00 --00 --00 151: --80 --80 --80 --80 --80 --80 128-mbit 256-mbit
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 100 order number: 306666, revision: 005 table 41. cfi link information offset (1) length description hex p = 10ah (optional flash features and commands) add. code value (p+48)h 4 cfi link field bit definitions 152: (p+49)h bits 0?9 = address offset (within 32mbit segment) of referenced cfi table 153: (p+4a)h bits 10?27 = nth 32mbit segment of referenced cfi table 154: (p+4b)h bits 28?30 = memory type 155: bit 31 = another cfi link field immediately follows (p+4c)h 1 cfi link field quantity subfield definitions 156: bits 0?3 = quantity field (n such that n+1 equals quantity) bit 4 = table & die relative location bit 5 = link field & table relative location bits 6?7 = reserved see table below see table below die 1 (b) die 2 (t) die 3 (b) die 4 (t) die 1 (t) die 2 (b) die 3 (t) die 4 (b) 152: --10 --ff --10 --ff --10 --ff --10 --ff 153: --20 --ff --20 --ff --20 --ff --20 --ff 154: --00 --ff --00 --ff --00 --ff --00 --ff 155: --00 --ff --00 --ff --00 --ff --00 --ff 156: --10 --ff --10 --ff --10 --ff --10 --ff address 1-gbit ?b ?t discrete ?b ?t ?- ?- die 1 (b) die 2 (t) die 1 (t) die 2 (b) 152: --ff --ff --10 --ff --10 --ff 153: --ff --ff --20 --ff --20 --ff 154: --ff --ff --00 --ff --00 --ff 155: --ff --ff --00 --ff --00 --ff 156: --ff --ff --10 --ff --10 --ff address 512-mbit ?b ?t
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 101 appendix d additional information order/document number document/tool 309045 p30 family specification update 308291 schematic review checklist for intel strataflash ? embedded memory (p30) 300783 using intel? flash memory: asynchronous page mode and synchronous burst mode 290667 intel strataflash ? memory (j3) datasheet 306667 migration guide for intel strataflash ? memory (j3) to intel strataflash ? embedded memory (p30) application note 812 290737 intel strataflash ? synchronous memory (k3/k18) datasheet 306669 migration guide for intel strataflash ? synchronous memory (k3/k18) to intel strataflash ? embedded memory (p30) application note 825 290701 intel ? wireless flash memory (w18) datasheet 290702 intel ? wireless flash memory (w30) datasheet 252802 intel ? flash memory design for a stacked chip scale package (scsp) 298161 intel ? flash memory chip scale package user?s guide 253418 intel ? wireless communications and computing package user's guide 296514 intel ? small outline package guide 297833 intel ? flash data integrator (intel ? fdi) user guide 298136 intel ? persistent storage manager (intel ? psm) user guide 306668 migration guide for spansion* s29glxxxn to intel strataflash ? embedded memory (p30) application note 813 notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel ? flash memory, visit our website at http://www.intel.com/go/choosesmart .
intel strataflash ? embedded memory (p30) family 08-feb-2006 intel strataflash ? embedded memory (p30) datasheet 102 order number: 306666, revision: 005 appendix e ordering information for discrete products figure 48. decoder for discrete intel strataflash ? embedded memory (p30) f 6 4 p 3 0 b 8 e 2 t 0 p roduct line designator 2 8f = intel? flash memory p ackage designator t e = 56-lead tsop, leaded j s = 56-lead tsop, lead-free r c = 64-ball easy bga, leaded p c = 64-ball easy bga, lead-free d evice density 6 40 = 64-mbit 1 28 = 128-mbit 2 56 = 256-mbit product family p30 = intel strataflash? embedded memor y v cc = 1.7 ? 2.0 v v ccq = 1.7 ? 3.6 v access speed 85 ns parameter location b = bottom parameter t = top parameter 8 5 table 42. valid combinations for discrete products 64-mbit 128-mbit 256-mbit te28f640p30b85 te28f128p30b85 te28f256p30b95 te28f640p30t85 te28f128p30t85 te28f256p30t95 js28f640p30b85 js28f128p30b85 js28f256p30b95 js28f640p30t85 js28f128p30t85 js28f256p30t95 rc28f640p30b85 rc28f128p30b85 rc28f256p30b85 rc28f640p30t85 rc28f128p30t85 rc28f256p30t85 pc28f640p30b85 pc28f128p30b85 pc28f256p30b85 pc28f640p30t85 pc28f128p30t85 pc28f256p30t85
intel strataflash ? embedded memory (p30) family datasheet intel strataflash ? embedded memory (p30) 08-feb-2006 order number: 306666, revision: 005 103 appendix f ordering information for scsp products figure 49. decoder for scsp intel strataflash ? embedded memory (p30) f 4 0 p 0 z b 8 d 4 r 0 0 q g roup designator 4 8f = flash memory only p ackage designator r d = intel ? scsp, leaded p f = intel ? scsp, lead-free r c = 64-ball easy bga, leaded p c = 64-ball easy bga, lead-free f lash density 0 = no die 2 = 64-mbit 3 = 128-mbit 4 = 256-mbit flash #1 flash #2 flash #3 flash #4 flash family 1 /2 flash family 3 /4 0 p roduct family p = intel strataflash? embedded memory 0 = no die device details 0 = original version of the product (refer to the latest version of the datasheet for details) ballout designator q = quad+ ballout 0 = discrete ballout parameter, mux configuration b = bottom parameter, non mux t = top parameter, non mux i/o voltage, ce# configuratio n z = individual chip enable(s) v = virtual chip enable(s) v cc = 1.7 v ? 2.0 v v ccq = 1.7 v ? 3.6 v table 43. valid combinations for stacked products 64-mbit 128-mbit 256-mbit 512-mbit rd48f2000p0zbq0 rd48f3000p0zbq0 rd48f4000p0zbq0 rd48f4400p0vbq0 rd48f2000p0ztq0 rd48f3000p0ztq0 rd48f4000p0ztq0 rd48f4400p0vtq0 pf48f2000p0zbq0 pf48f3000p0zbq0 pf48f4000p0zbq0 pf48f4400p0vbq0 pf48f2000p0ztq0 pf48f3000p0ztq0 pf48f4000p0ztq0 pf48f4400p0vtq0 rc48f4400p0vb00 rc48f4400p0vt00 pc48f4400p0vb00 pc48f4400p0vt00

▲Up To Search▲

Price & Availability of PC48F4400P0VT00A

	To Download PC48F4400P0VT00A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .